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From: CK Hu <ck.hu@mediatek.com>
To: Stu Hsieh <stu.hsieh@mediatek.com>
Cc: Philipp Zabel <p.zabel@pengutronix.de>,
	David Airlie <airlied@linux.ie>, Rob Herring <robh+dt@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>,
	Matthias Brugger <matthias.bgg@gmail.com>,
	<dri-devel@lists.freedesktop.org>, <devicetree@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-mediatek@lists.infradead.org>,
	<srv_heupstream@mediatek.com>
Subject: Re: [PATCH 19/28] drm/mediatek: add connection from RDMA2 to DPI1
Date: Wed, 13 Jun 2018 17:01:01 +0800	[thread overview]
Message-ID: <1528880461.18148.1.camel@mtksdaap41> (raw)
In-Reply-To: <1528880291.11190.45.camel@mtksdccf07>

Hi, Stu:

On Wed, 2018-06-13 at 16:58 +0800, Stu Hsieh wrote:
> Hi, CK:
> 
> On Wed, 2018-06-13 at 16:14 +0800, CK Hu wrote:
> > Hi, Stu:
> > 
> > On Wed, 2018-06-13 at 16:01 +0800, Stu Hsieh wrote:
> > > Hi, CK:
> > > 
> > > 
> > > On Wed, 2018-06-13 at 15:13 +0800, CK Hu wrote:
> > > > Hi, Stu:
> > > > 
> > > > On Mon, 2018-06-11 at 11:26 +0800, Stu Hsieh wrote:
> > > > > This patch add the connection from RDMA2 to DPI1
> > > > > 
> > > > > Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
> > > > > ---
> > > > >  drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 8 ++++++++
> > > > >  1 file changed, 8 insertions(+)
> > > > > 
> > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> > > > > index 31a0832ef9ec..2d883815d79c 100644
> > > > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> > > > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> > > > > @@ -93,9 +93,11 @@
> > > > >  #define RDMA1_MOUT_DPI0			0x2
> > > > >  #define RDMA1_MOUT_DPI1			0x3
> > > > >  #define RDMA2_MOUT_DPI0			0x2
> > > > > +#define RDMA2_MOUT_DPI1			0x3
> > > > 
> > > > Usually, each bit of a mout register represent a output enable. Is this
> > > > value 0x3 a correct value?
> > > > 
> > > > Regards,
> > > > CK
> > > > 
> > > In HW CONFIG SPEC or MT2712_E2_MMSYS_Change_note show as following:
> > > 
> > > Bit(s)	Name			Description
> > > 2:0	DISP_RDMA2_SOUT_SEL_IN	0: output to dsi0
> > > 				1: outptu to dsi1
> > > 				2: output to dpi0
> > > 				3: output to dpi1
> > > 				4: output to dsi2
> > > 				5: output to dsi3
> > > 
> > > So, 0x3 is correct value.
> > 
> > The data sheet use the term SOUT match its function, so I think driver
> > have better change the naming to SOUT.
> > 
> > Regards,
> > CK
> > 
> 
> The definition DISP_REG_CONFIG_DISP_RDMA2_SOUT is use term SOUT in this
> patch.
> 

I know, but RDMA2_MOUT_DPI1 should be changed to RDMA2_SOUT_DPI1.

Regards,
CK

> Regard,
> Stu
> 
> > > 
> > > Regard,
> > > Stu
> > > 
> > > > >  #define DPI0_SEL_IN_RDMA1		0x1
> > > > >  #define DPI0_SEL_IN_RDMA2		0x3
> > > > >  #define DPI1_SEL_IN_RDMA1		(0x1 << 8)
> > > > > +#define DPI1_SEL_IN_RDMA2		(0x3 << 8)
> > > > >  #define DSI1_SEL_IN_RDMA1		0x1
> > > > >  #define DSI2_SEL_IN_RDMA1		(0x1 << 16)
> > > > >  #define DSI3_SEL_IN_RDMA1		(0x1 << 16)
> > > > > @@ -199,6 +201,9 @@ static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur,
> > > > >  	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
> > > > >  		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> > > > >  		value = RDMA2_MOUT_DPI0;
> > > > > +	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
> > > > > +		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> > > > > +		value = RDMA2_MOUT_DPI1;
> > > > >  	} else {
> > > > >  		value = 0;
> > > > >  	}
> > > > > @@ -233,6 +238,9 @@ static unsigned int mtk_ddp_sel_in(enum mtk_ddp_comp_id cur,
> > > > >  	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
> > > > >  		*addr = DISP_REG_CONFIG_DPI_SEL_IN;
> > > > >  		value = DPI0_SEL_IN_RDMA2;
> > > > > +	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
> > > > > +		*addr = DISP_REG_CONFIG_DPI_SEL_IN;
> > > > > +		value = DPI1_SEL_IN_RDMA2;
> > > > >  	} else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
> > > > >  		*addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
> > > > >  		value = COLOR1_SEL_IN_OVL1;
> > > > 
> > > > 
> > > 
> > > 
> > 
> > 
> 
> 



WARNING: multiple messages have this Message-ID (diff)
From: CK Hu <ck.hu@mediatek.com>
To: Stu Hsieh <stu.hsieh@mediatek.com>
Cc: Mark Rutland <mark.rutland@arm.com>,
	devicetree@vger.kernel.org, srv_heupstream@mediatek.com,
	David Airlie <airlied@linux.ie>,
	linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
	Rob Herring <robh+dt@kernel.org>,
	linux-mediatek@lists.infradead.org,
	Matthias Brugger <matthias.bgg@gmail.com>,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 19/28] drm/mediatek: add connection from RDMA2 to DPI1
Date: Wed, 13 Jun 2018 17:01:01 +0800	[thread overview]
Message-ID: <1528880461.18148.1.camel@mtksdaap41> (raw)
In-Reply-To: <1528880291.11190.45.camel@mtksdccf07>

Hi, Stu:

On Wed, 2018-06-13 at 16:58 +0800, Stu Hsieh wrote:
> Hi, CK:
> 
> On Wed, 2018-06-13 at 16:14 +0800, CK Hu wrote:
> > Hi, Stu:
> > 
> > On Wed, 2018-06-13 at 16:01 +0800, Stu Hsieh wrote:
> > > Hi, CK:
> > > 
> > > 
> > > On Wed, 2018-06-13 at 15:13 +0800, CK Hu wrote:
> > > > Hi, Stu:
> > > > 
> > > > On Mon, 2018-06-11 at 11:26 +0800, Stu Hsieh wrote:
> > > > > This patch add the connection from RDMA2 to DPI1
> > > > > 
> > > > > Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
> > > > > ---
> > > > >  drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 8 ++++++++
> > > > >  1 file changed, 8 insertions(+)
> > > > > 
> > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> > > > > index 31a0832ef9ec..2d883815d79c 100644
> > > > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> > > > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> > > > > @@ -93,9 +93,11 @@
> > > > >  #define RDMA1_MOUT_DPI0			0x2
> > > > >  #define RDMA1_MOUT_DPI1			0x3
> > > > >  #define RDMA2_MOUT_DPI0			0x2
> > > > > +#define RDMA2_MOUT_DPI1			0x3
> > > > 
> > > > Usually, each bit of a mout register represent a output enable. Is this
> > > > value 0x3 a correct value?
> > > > 
> > > > Regards,
> > > > CK
> > > > 
> > > In HW CONFIG SPEC or MT2712_E2_MMSYS_Change_note show as following:
> > > 
> > > Bit(s)	Name			Description
> > > 2:0	DISP_RDMA2_SOUT_SEL_IN	0: output to dsi0
> > > 				1: outptu to dsi1
> > > 				2: output to dpi0
> > > 				3: output to dpi1
> > > 				4: output to dsi2
> > > 				5: output to dsi3
> > > 
> > > So, 0x3 is correct value.
> > 
> > The data sheet use the term SOUT match its function, so I think driver
> > have better change the naming to SOUT.
> > 
> > Regards,
> > CK
> > 
> 
> The definition DISP_REG_CONFIG_DISP_RDMA2_SOUT is use term SOUT in this
> patch.
> 

I know, but RDMA2_MOUT_DPI1 should be changed to RDMA2_SOUT_DPI1.

Regards,
CK

> Regard,
> Stu
> 
> > > 
> > > Regard,
> > > Stu
> > > 
> > > > >  #define DPI0_SEL_IN_RDMA1		0x1
> > > > >  #define DPI0_SEL_IN_RDMA2		0x3
> > > > >  #define DPI1_SEL_IN_RDMA1		(0x1 << 8)
> > > > > +#define DPI1_SEL_IN_RDMA2		(0x3 << 8)
> > > > >  #define DSI1_SEL_IN_RDMA1		0x1
> > > > >  #define DSI2_SEL_IN_RDMA1		(0x1 << 16)
> > > > >  #define DSI3_SEL_IN_RDMA1		(0x1 << 16)
> > > > > @@ -199,6 +201,9 @@ static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur,
> > > > >  	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
> > > > >  		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> > > > >  		value = RDMA2_MOUT_DPI0;
> > > > > +	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
> > > > > +		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> > > > > +		value = RDMA2_MOUT_DPI1;
> > > > >  	} else {
> > > > >  		value = 0;
> > > > >  	}
> > > > > @@ -233,6 +238,9 @@ static unsigned int mtk_ddp_sel_in(enum mtk_ddp_comp_id cur,
> > > > >  	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
> > > > >  		*addr = DISP_REG_CONFIG_DPI_SEL_IN;
> > > > >  		value = DPI0_SEL_IN_RDMA2;
> > > > > +	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
> > > > > +		*addr = DISP_REG_CONFIG_DPI_SEL_IN;
> > > > > +		value = DPI1_SEL_IN_RDMA2;
> > > > >  	} else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
> > > > >  		*addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
> > > > >  		value = COLOR1_SEL_IN_OVL1;
> > > > 
> > > > 
> > > 
> > > 
> > 
> > 
> 
> 


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WARNING: multiple messages have this Message-ID (diff)
From: ck.hu@mediatek.com (CK Hu)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 19/28] drm/mediatek: add connection from RDMA2 to DPI1
Date: Wed, 13 Jun 2018 17:01:01 +0800	[thread overview]
Message-ID: <1528880461.18148.1.camel@mtksdaap41> (raw)
In-Reply-To: <1528880291.11190.45.camel@mtksdccf07>

Hi, Stu:

On Wed, 2018-06-13 at 16:58 +0800, Stu Hsieh wrote:
> Hi, CK:
> 
> On Wed, 2018-06-13 at 16:14 +0800, CK Hu wrote:
> > Hi, Stu:
> > 
> > On Wed, 2018-06-13 at 16:01 +0800, Stu Hsieh wrote:
> > > Hi, CK:
> > > 
> > > 
> > > On Wed, 2018-06-13 at 15:13 +0800, CK Hu wrote:
> > > > Hi, Stu:
> > > > 
> > > > On Mon, 2018-06-11 at 11:26 +0800, Stu Hsieh wrote:
> > > > > This patch add the connection from RDMA2 to DPI1
> > > > > 
> > > > > Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
> > > > > ---
> > > > >  drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 8 ++++++++
> > > > >  1 file changed, 8 insertions(+)
> > > > > 
> > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> > > > > index 31a0832ef9ec..2d883815d79c 100644
> > > > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> > > > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> > > > > @@ -93,9 +93,11 @@
> > > > >  #define RDMA1_MOUT_DPI0			0x2
> > > > >  #define RDMA1_MOUT_DPI1			0x3
> > > > >  #define RDMA2_MOUT_DPI0			0x2
> > > > > +#define RDMA2_MOUT_DPI1			0x3
> > > > 
> > > > Usually, each bit of a mout register represent a output enable. Is this
> > > > value 0x3 a correct value?
> > > > 
> > > > Regards,
> > > > CK
> > > > 
> > > In HW CONFIG SPEC or MT2712_E2_MMSYS_Change_note show as following:
> > > 
> > > Bit(s)	Name			Description
> > > 2:0	DISP_RDMA2_SOUT_SEL_IN	0: output to dsi0
> > > 				1: outptu to dsi1
> > > 				2: output to dpi0
> > > 				3: output to dpi1
> > > 				4: output to dsi2
> > > 				5: output to dsi3
> > > 
> > > So, 0x3 is correct value.
> > 
> > The data sheet use the term SOUT match its function, so I think driver
> > have better change the naming to SOUT.
> > 
> > Regards,
> > CK
> > 
> 
> The definition DISP_REG_CONFIG_DISP_RDMA2_SOUT is use term SOUT in this
> patch.
> 

I know, but RDMA2_MOUT_DPI1 should be changed to RDMA2_SOUT_DPI1.

Regards,
CK

> Regard,
> Stu
> 
> > > 
> > > Regard,
> > > Stu
> > > 
> > > > >  #define DPI0_SEL_IN_RDMA1		0x1
> > > > >  #define DPI0_SEL_IN_RDMA2		0x3
> > > > >  #define DPI1_SEL_IN_RDMA1		(0x1 << 8)
> > > > > +#define DPI1_SEL_IN_RDMA2		(0x3 << 8)
> > > > >  #define DSI1_SEL_IN_RDMA1		0x1
> > > > >  #define DSI2_SEL_IN_RDMA1		(0x1 << 16)
> > > > >  #define DSI3_SEL_IN_RDMA1		(0x1 << 16)
> > > > > @@ -199,6 +201,9 @@ static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur,
> > > > >  	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
> > > > >  		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> > > > >  		value = RDMA2_MOUT_DPI0;
> > > > > +	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
> > > > > +		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> > > > > +		value = RDMA2_MOUT_DPI1;
> > > > >  	} else {
> > > > >  		value = 0;
> > > > >  	}
> > > > > @@ -233,6 +238,9 @@ static unsigned int mtk_ddp_sel_in(enum mtk_ddp_comp_id cur,
> > > > >  	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
> > > > >  		*addr = DISP_REG_CONFIG_DPI_SEL_IN;
> > > > >  		value = DPI0_SEL_IN_RDMA2;
> > > > > +	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
> > > > > +		*addr = DISP_REG_CONFIG_DPI_SEL_IN;
> > > > > +		value = DPI1_SEL_IN_RDMA2;
> > > > >  	} else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
> > > > >  		*addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
> > > > >  		value = COLOR1_SEL_IN_OVL1;
> > > > 
> > > > 
> > > 
> > > 
> > 
> > 
> 
> 

  reply	other threads:[~2018-06-13  9:01 UTC|newest]

Thread overview: 189+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-06-11  3:25 [PATCH v5 00/28] Add support for mediatek SOC MT2712 Stu Hsieh
2018-06-11  3:25 ` Stu Hsieh
2018-06-11  3:25 ` Stu Hsieh
2018-06-11  3:25 ` [PATCH 01/28] drm/mediatek: update dt-bindings for mt2712 Stu Hsieh
2018-06-11  3:25   ` Stu Hsieh
2018-06-11  3:25   ` Stu Hsieh
2018-06-11  3:25 ` [PATCH 02/28] drm/mediatek: support maximum 64 mutex mod Stu Hsieh
2018-06-11  3:25   ` Stu Hsieh
2018-06-11  3:25   ` Stu Hsieh
2018-06-11  3:25 ` [PATCH 03/28] drm/mediatek: add ddp component AAL1 Stu Hsieh
2018-06-11  3:25   ` Stu Hsieh
2018-06-11  3:25   ` Stu Hsieh
2018-06-11  3:25 ` [PATCH 04/28] drm/mediatek: add ddp component OD1 Stu Hsieh
2018-06-11  3:25   ` Stu Hsieh
2018-06-11  3:25   ` Stu Hsieh
2018-06-13  5:27   ` CK Hu
2018-06-13  5:27     ` CK Hu
2018-06-13  5:27     ` CK Hu
2018-06-11  3:25 ` [PATCH 05/28] drm/mediatek: add ddp component PWM1 Stu Hsieh
2018-06-11  3:25   ` Stu Hsieh
2018-06-11  3:25   ` Stu Hsieh
2018-06-11  3:25 ` [PATCH 06/28] drm/mediatek: add ddp component PWM2 Stu Hsieh
2018-06-11  3:25   ` Stu Hsieh
2018-06-11  3:25   ` Stu Hsieh
2018-06-11  3:25 ` [PATCH 07/28] drm/mediatek: add component DPI1 Stu Hsieh
2018-06-11  3:25   ` Stu Hsieh
2018-06-11  3:25   ` Stu Hsieh
2018-06-13  5:29   ` CK Hu
2018-06-13  5:29     ` CK Hu
2018-06-13  5:29     ` CK Hu
2018-06-11  3:26 ` [PATCH 08/28] drm/mediatek: add component DSI2 Stu Hsieh
2018-06-11  3:26   ` Stu Hsieh
2018-06-11  3:26   ` Stu Hsieh
2018-06-13  5:30   ` CK Hu
2018-06-13  5:30     ` CK Hu
2018-06-13  5:30     ` CK Hu
2018-06-11  3:26 ` [PATCH 09/28] drm/mediatek: add component DSI3 Stu Hsieh
2018-06-11  3:26   ` Stu Hsieh
2018-06-11  3:26   ` Stu Hsieh
2018-06-13  5:31   ` CK Hu
2018-06-13  5:31     ` CK Hu
2018-06-13  5:31     ` CK Hu
2018-06-11  3:26 ` [PATCH 10/28] drm/mediatek: add connection from OD1 to RDMA1 Stu Hsieh
2018-06-11  3:26   ` Stu Hsieh
2018-06-11  3:26   ` Stu Hsieh
2018-06-11  3:26 ` [PATCH 11/28] drm/mediatek: add connection from RDMA0 to DPI0 Stu Hsieh
2018-06-11  3:26   ` Stu Hsieh
2018-06-11  3:26   ` Stu Hsieh
2018-06-13  5:38   ` CK Hu
2018-06-13  5:38     ` CK Hu
2018-06-13  5:38     ` CK Hu
2018-06-11  3:26 ` [PATCH 12/28] drm/mediatek: add connection from RDMA0 to DSI2 Stu Hsieh
2018-06-11  3:26   ` Stu Hsieh
2018-06-11  3:26   ` Stu Hsieh
2018-06-13  5:39   ` CK Hu
2018-06-13  5:39     ` CK Hu
2018-06-13  5:39     ` CK Hu
2018-06-11  3:26 ` [PATCH 13/28] drm/mediatek: add connection from RDMA0 to DSI3 Stu Hsieh
2018-06-11  3:26   ` Stu Hsieh
2018-06-11  3:26   ` Stu Hsieh
2018-06-13  5:45   ` CK Hu
2018-06-13  5:45     ` CK Hu
2018-06-13  5:45     ` CK Hu
2018-06-13  7:46     ` Stu Hsieh
2018-06-13  7:46       ` Stu Hsieh
2018-06-13  7:46       ` Stu Hsieh
2018-06-13  8:05       ` CK Hu
2018-06-13  8:05         ` CK Hu
2018-06-13  8:05         ` CK Hu
2018-06-13  8:52         ` Stu Hsieh
2018-06-13  8:52           ` Stu Hsieh
2018-06-13  8:52           ` Stu Hsieh
2018-06-11  3:26 ` [PATCH 14/28] drm/mediatek: add connection from RDMA1 to DPI1 Stu Hsieh
2018-06-11  3:26   ` Stu Hsieh
2018-06-11  3:26   ` Stu Hsieh
2018-06-13  6:13   ` CK Hu
2018-06-13  6:13     ` CK Hu
2018-06-13  6:13     ` CK Hu
2018-06-13  7:56     ` Stu Hsieh
2018-06-13  7:56       ` Stu Hsieh
2018-06-13  7:56       ` Stu Hsieh
2018-06-13  8:27       ` CK Hu
2018-06-13  8:27         ` CK Hu
2018-06-13  8:27         ` CK Hu
2018-06-13  8:53         ` Stu Hsieh
2018-06-13  8:53           ` Stu Hsieh
2018-06-13  8:53           ` Stu Hsieh
2018-06-11  3:26 ` [PATCH 15/28] drm/mediatek: add connection from RDMA1 to DSI1 Stu Hsieh
2018-06-11  3:26   ` Stu Hsieh
2018-06-11  3:26   ` Stu Hsieh
2018-06-13  6:44   ` CK Hu
2018-06-13  6:44     ` CK Hu
2018-06-13  6:44     ` CK Hu
2018-06-13  6:59     ` CK Hu
2018-06-13  6:59       ` CK Hu
2018-06-13  6:59       ` CK Hu
2018-06-11  3:26 ` [PATCH 16/28] drm/mediatek: add connection from RDMA1 to DSI2 Stu Hsieh
2018-06-11  3:26   ` Stu Hsieh
2018-06-11  3:26   ` Stu Hsieh
2018-06-13  7:00   ` CK Hu
2018-06-13  7:00     ` CK Hu
2018-06-13  7:00     ` CK Hu
2018-06-11  3:26 ` [PATCH 17/28] drm/mediatek: add connection from RDMA1 to DSI3 Stu Hsieh
2018-06-11  3:26   ` Stu Hsieh
2018-06-11  3:26   ` Stu Hsieh
2018-06-13  7:04   ` CK Hu
2018-06-13  7:04     ` CK Hu
2018-06-13  7:04     ` CK Hu
2018-06-11  3:26 ` [PATCH 18/28] drm/mediatek: add connection from RDMA2 to DPI0 Stu Hsieh
2018-06-11  3:26   ` Stu Hsieh
2018-06-11  3:26   ` Stu Hsieh
2018-06-13  7:07   ` CK Hu
2018-06-13  7:07     ` CK Hu
2018-06-13  7:07     ` CK Hu
2018-06-11  3:26 ` [PATCH 19/28] drm/mediatek: add connection from RDMA2 to DPI1 Stu Hsieh
2018-06-11  3:26   ` Stu Hsieh
2018-06-11  3:26   ` Stu Hsieh
2018-06-13  7:13   ` CK Hu
2018-06-13  7:13     ` CK Hu
2018-06-13  7:13     ` CK Hu
2018-06-13  8:01     ` Stu Hsieh
2018-06-13  8:01       ` Stu Hsieh
2018-06-13  8:01       ` Stu Hsieh
2018-06-13  8:14       ` CK Hu
2018-06-13  8:14         ` CK Hu
2018-06-13  8:14         ` CK Hu
2018-06-13  8:58         ` Stu Hsieh
2018-06-13  8:58           ` Stu Hsieh
2018-06-13  8:58           ` Stu Hsieh
2018-06-13  9:01           ` CK Hu [this message]
2018-06-13  9:01             ` CK Hu
2018-06-13  9:01             ` CK Hu
2018-06-11  3:26 ` [PATCH 20/28] drm/mediatek: add connection from RDMA2 to DSI1 Stu Hsieh
2018-06-11  3:26   ` Stu Hsieh
2018-06-11  3:26   ` Stu Hsieh
2018-06-13  7:17   ` CK Hu
2018-06-13  7:17     ` CK Hu
2018-06-13  7:17     ` CK Hu
2018-06-11  3:26 ` [PATCH 21/28] drm/mediatek: add connection from RDMA2 to DSI2 Stu Hsieh
2018-06-11  3:26   ` Stu Hsieh
2018-06-11  3:26   ` Stu Hsieh
2018-06-13  7:18   ` CK Hu
2018-06-13  7:18     ` CK Hu
2018-06-13  7:18     ` CK Hu
2018-06-11  3:26 ` [PATCH 22/28] drm/mediatek: add connection from RDMA2 to DSI3 Stu Hsieh
2018-06-11  3:26   ` Stu Hsieh
2018-06-11  3:26   ` Stu Hsieh
2018-06-13  7:19   ` CK Hu
2018-06-13  7:19     ` CK Hu
2018-06-13  7:19     ` CK Hu
2018-06-11  3:26 ` [PATCH 23/28] drm/mediatek: add DPI1 support for mutex Stu Hsieh
2018-06-11  3:26   ` Stu Hsieh
2018-06-11  3:26   ` Stu Hsieh
2018-06-13  7:22   ` CK Hu
2018-06-13  7:22     ` CK Hu
2018-06-13  7:22     ` CK Hu
2018-06-11  3:26 ` [PATCH 24/28] drm/mediatek: add DSI2 " Stu Hsieh
2018-06-11  3:26   ` Stu Hsieh
2018-06-11  3:26   ` Stu Hsieh
2018-06-13  7:22   ` CK Hu
2018-06-13  7:22     ` CK Hu
2018-06-13  7:22     ` CK Hu
2018-06-11  3:26 ` [PATCH 25/28] drm/mediatek: add DSI3 " Stu Hsieh
2018-06-11  3:26   ` Stu Hsieh
2018-06-11  3:26   ` Stu Hsieh
2018-06-13  7:22   ` CK Hu
2018-06-13  7:22     ` CK Hu
2018-06-13  7:22     ` CK Hu
2018-06-11  3:26 ` [PATCH 26/28] drm/mediatek: add DPI1/DSI1/DSI2/DSI3 in comp_init Stu Hsieh
2018-06-11  3:26   ` Stu Hsieh
2018-06-11  3:26   ` Stu Hsieh
2018-06-13  7:35   ` CK Hu
2018-06-13  7:35     ` CK Hu
2018-06-13  7:35     ` CK Hu
2018-06-13  8:05     ` Stu Hsieh
2018-06-13  8:05       ` Stu Hsieh
2018-06-13  8:05       ` Stu Hsieh
2018-06-11  3:26 ` [PATCH 27/28] drm/mediatek: add third ddp path Stu Hsieh
2018-06-11  3:26   ` Stu Hsieh
2018-06-11  3:26   ` Stu Hsieh
2018-06-13  7:38   ` CK Hu
2018-06-13  7:38     ` CK Hu
2018-06-13  7:38     ` CK Hu
2018-06-11  3:26 ` [PATCH 28/28] drm/mediatek: Add support for mediatek SOC MT2712 Stu Hsieh
2018-06-11  3:26   ` Stu Hsieh
2018-06-11  3:26   ` Stu Hsieh
2018-06-13  7:48   ` CK Hu
2018-06-13  7:48     ` CK Hu
2018-06-13  7:48     ` CK Hu

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