Re: [PATCH v3 3/3] PCI: imx6: Add support for i.MX8MQ

From: Trent Piepho <tpiepho@impinj.com>
To: "l.stach@pengutronix.de" <l.stach@pengutronix.de>,
	"andrew.smirnov@gmail.com" <andrew.smirnov@gmail.com>
Cc: "aisheng.dong@nxp.com" <aisheng.dong@nxp.com>,
	"hongxing.zhu@nxp.com" <hongxing.zhu@nxp.com>,
	"cphealy@gmail.com" <cphealy@gmail.com>,
	"linux-imx@nxp.com" <linux-imx@nxp.com>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	"lorenzo.pieralisi@arm.com" <lorenzo.pieralisi@arm.com>,
	"fabio.estevam@nxp.com" <fabio.estevam@nxp.com>,
	"robh@kernel.org" <robh@kernel.org>,
	"linux-arm-kernel@lists.infradead.org" 
	<linux-arm-kernel@lists.infradead.org>,
	"bhelgaas@google.com" <bhelgaas@google.com>,
	"leonard.crestez@nxp.com" <leonard.crestez@nxp.com>,
	"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>
Subject: Re: [PATCH v3 3/3] PCI: imx6: Add support for i.MX8MQ
Date: Thu, 20 Dec 2018 01:22:51 +0000	[thread overview]
Message-ID: <1545268969.22930.77.camel@impinj.com> (raw)
In-Reply-To: <CAHQ1cqEMxxo9JGN5be4XQWAtPz7nC2JyLCr3qasnD5QK7_hOYQ@mail.gmail.com>

On Wed, 2018-12-19 at 16:47 -0800, Andrey Smirnov wrote:
> 
> > > This series initially added explicit offsets but I suggested a single
> > > "controller-id" because:
> > >   * There are multiple bit and byte offsets
> > >   * Other imx8 SOCs also have 2x pcie with other bit/byte offsets
> > > 
> > > Hiding this behind a compatible string and single "controller-id" seem
> > > preferable to elaborating register maps in dt bindings. It also makes
> > > upgrades simpler: if features are added which use other bits there is no
> > > need to describe them in DT and deal with compatibility headaches.
> > 
> > You already have an id for the controllers: the address. Use that if
> > you don't want to put the register offsets in DT.
> > 
> 
> Lucas, are you on board with this?

Does address here mean the address from the controller's reg property?

How do you map that address to the controller's index?  A giant table
of every soc so the soc type plus controller register address pair than
can be looked up in the driver?

I.e., on iMX8MQ the controller at 0x33800000 is controller 0 and so on
for every possible SoC address combination?

Not really a fan of that.

The situation here is that some registers for these controllers are
interleaved, right?  I.e., there's one register somewhere where bit 0
means enable controller 0 and bit 1 means enable controller 1 and so
on.

Isn't cell-index already the standard device tree property for this
kind of setup?

I know cell-index was historically also (ab)used in an attempt to
provide a fixed kernel device enumeration order, something now handled
better by chosen node aliases.