From: Weiyi Lu <weiyi.lu@mediatek.com>
To: Stephen Boyd <sboyd@codeaurora.org>
Cc: Nicolas Boichat <drinkcat@chromium.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
Rob Herring <robh@kernel.org>,
James Liao <jamesjj.liao@mediatek.com>,
Fan Chen <fan.chen@mediatek.com>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>,
<linux-mediatek@lists.infradead.org>, <linux-clk@vger.kernel.org>,
<srv_heupstream@mediatek.com>, <stable@vger.kernel.org>
Subject: Re: [PATCH v5 0/9] Mediatek MT8183 clock support
Date: Thu, 28 Mar 2019 13:18:20 +0800 [thread overview]
Message-ID: <1553750300.20204.2.camel@mtksdaap41> (raw)
In-Reply-To: <20190305050546.23431-1-weiyi.lu@mediatek.com>
On Tue, 2019-03-05 at 13:05 +0800, Weiyi Lu wrote:
Hi Stephen,
Just gentle ping. Many thanks.
> Resend clock patches from v4 based on v5.0-rc1.
>
> The whole series now is composed of
> a fix for PLL tuner (PATCH 1),
> clock common changes for both MT8183 & MT6765 (PATCH 2-3),
> clock support of MT8183 (PATCH 4-8) and
> resend a clock patch long time ago(PTACH 9).
>
> changes since v4:
> - refine for the fix of PLL tuner(PATCH 1).
> - add configurable pcw_chg_reg for MT8183 and the following IC(PATCH 7).
>
> changes sinve v3:
> - add fix tag.
> - small change of mtk_clk_mux data structure.
> - use of_property_for_each_string to iterate dependent subsys clock of power domain.
> - document critical clocks.
> - reduce some clock register error log.
> - few coding style fix.
>
> changes sinve v2:
> - refine for implementation consistency of mtk clk mux.
> - separate the onoff API into enable/disable API for mtk scpsys.
> - resend a patch about PLL rate changing.
>
> changes since v1:
> - refine for better code quality.
> - some minor bug fix of clock part, like incorrect control address
> and missing clocks.
>
>
WARNING: multiple messages have this Message-ID (diff)
From: Weiyi Lu <weiyi.lu@mediatek.com>
To: Stephen Boyd <sboyd@codeaurora.org>
Cc: Nicolas Boichat <drinkcat@chromium.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
Rob Herring <robh@kernel.org>,
James Liao <jamesjj.liao@mediatek.com>,
Fan Chen <fan.chen@mediatek.com>,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
linux-clk@vger.kernel.org, srv_heupstream@mediatek.com,
stable@vger.kernel.org
Subject: Re: [PATCH v5 0/9] Mediatek MT8183 clock support
Date: Thu, 28 Mar 2019 13:18:20 +0800 [thread overview]
Message-ID: <1553750300.20204.2.camel@mtksdaap41> (raw)
In-Reply-To: <20190305050546.23431-1-weiyi.lu@mediatek.com>
On Tue, 2019-03-05 at 13:05 +0800, Weiyi Lu wrote:
Hi Stephen,
Just gentle ping. Many thanks.
> Resend clock patches from v4 based on v5.0-rc1.
>
> The whole series now is composed of
> a fix for PLL tuner (PATCH 1),
> clock common changes for both MT8183 & MT6765 (PATCH 2-3),
> clock support of MT8183 (PATCH 4-8) and
> resend a clock patch long time ago(PTACH 9).
>
> changes since v4:
> - refine for the fix of PLL tuner(PATCH 1).
> - add configurable pcw_chg_reg for MT8183 and the following IC(PATCH 7).
>
> changes sinve v3:
> - add fix tag.
> - small change of mtk_clk_mux data structure.
> - use of_property_for_each_string to iterate dependent subsys clock of power domain.
> - document critical clocks.
> - reduce some clock register error log.
> - few coding style fix.
>
> changes sinve v2:
> - refine for implementation consistency of mtk clk mux.
> - separate the onoff API into enable/disable API for mtk scpsys.
> - resend a patch about PLL rate changing.
>
> changes since v1:
> - refine for better code quality.
> - some minor bug fix of clock part, like incorrect control address
> and missing clocks.
>
>
WARNING: multiple messages have this Message-ID (diff)
From: Weiyi Lu <weiyi.lu@mediatek.com>
To: Stephen Boyd <sboyd@codeaurora.org>
Cc: Rob Herring <robh@kernel.org>,
Nicolas Boichat <drinkcat@chromium.org>,
srv_heupstream@mediatek.com,
James Liao <jamesjj.liao@mediatek.com>,
linux-kernel@vger.kernel.org, stable@vger.kernel.org,
Fan Chen <fan.chen@mediatek.com>,
linux-mediatek@lists.infradead.org,
Matthias Brugger <matthias.bgg@gmail.com>,
linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v5 0/9] Mediatek MT8183 clock support
Date: Thu, 28 Mar 2019 13:18:20 +0800 [thread overview]
Message-ID: <1553750300.20204.2.camel@mtksdaap41> (raw)
In-Reply-To: <20190305050546.23431-1-weiyi.lu@mediatek.com>
On Tue, 2019-03-05 at 13:05 +0800, Weiyi Lu wrote:
Hi Stephen,
Just gentle ping. Many thanks.
> Resend clock patches from v4 based on v5.0-rc1.
>
> The whole series now is composed of
> a fix for PLL tuner (PATCH 1),
> clock common changes for both MT8183 & MT6765 (PATCH 2-3),
> clock support of MT8183 (PATCH 4-8) and
> resend a clock patch long time ago(PTACH 9).
>
> changes since v4:
> - refine for the fix of PLL tuner(PATCH 1).
> - add configurable pcw_chg_reg for MT8183 and the following IC(PATCH 7).
>
> changes sinve v3:
> - add fix tag.
> - small change of mtk_clk_mux data structure.
> - use of_property_for_each_string to iterate dependent subsys clock of power domain.
> - document critical clocks.
> - reduce some clock register error log.
> - few coding style fix.
>
> changes sinve v2:
> - refine for implementation consistency of mtk clk mux.
> - separate the onoff API into enable/disable API for mtk scpsys.
> - resend a patch about PLL rate changing.
>
> changes since v1:
> - refine for better code quality.
> - some minor bug fix of clock part, like incorrect control address
> and missing clocks.
>
>
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next prev parent reply other threads:[~2019-03-28 5:18 UTC|newest]
Thread overview: 116+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-05 5:05 [PATCH v5 0/9] Mediatek MT8183 clock support Weiyi Lu
2019-03-05 5:05 ` Weiyi Lu
2019-03-05 5:05 ` Weiyi Lu
2019-03-05 5:05 ` Weiyi Lu
2019-03-05 5:05 ` Weiyi Lu
2019-03-05 5:05 ` Weiyi Lu
2019-03-05 18:41 ` Stephen Boyd
2019-03-05 18:41 ` Stephen Boyd
2019-03-05 18:41 ` Stephen Boyd
2019-03-05 5:05 ` [PATCH v5 1/9] clk: mediatek: Disable tuner_en before change PLL rate Weiyi Lu
2019-03-05 5:05 ` Weiyi Lu
2019-03-05 5:05 ` Weiyi Lu
2019-03-05 6:42 ` James Liao
2019-03-05 6:42 ` James Liao
2019-03-05 6:42 ` James Liao
2019-03-07 16:09 ` Matthias Brugger
2019-03-07 16:09 ` Matthias Brugger
2019-04-11 20:16 ` Stephen Boyd
2019-04-11 20:16 ` Stephen Boyd
2019-04-11 20:16 ` Stephen Boyd
2019-03-05 5:05 ` [PATCH v5 2/9] clk: mediatek: Add new clkmux register API Weiyi Lu
2019-03-05 5:05 ` Weiyi Lu
2019-03-05 5:05 ` Weiyi Lu
2019-03-05 6:43 ` James Liao
2019-03-05 6:43 ` James Liao
2019-03-05 6:43 ` James Liao
2019-03-08 6:17 ` Nicolas Boichat
2019-03-08 6:17 ` Nicolas Boichat
2019-03-08 6:17 ` Nicolas Boichat
2019-03-14 23:21 ` Nicolas Boichat
2019-03-14 23:21 ` Nicolas Boichat
2019-03-14 23:21 ` Nicolas Boichat
2019-04-11 20:12 ` Stephen Boyd
2019-04-11 20:12 ` Stephen Boyd
2019-04-11 20:12 ` Stephen Boyd
2019-04-11 20:16 ` Stephen Boyd
2019-04-11 20:16 ` Stephen Boyd
2019-04-11 20:16 ` Stephen Boyd
2019-03-05 5:05 ` [PATCH v5 3/9] clk: mediatek: Add configurable pcwibits and fmin to mtk_pll_data Weiyi Lu
2019-03-05 5:05 ` Weiyi Lu
2019-03-05 5:05 ` Weiyi Lu
2019-03-05 6:46 ` James Liao
2019-03-05 6:46 ` James Liao
2019-03-05 6:46 ` James Liao
2019-03-08 6:20 ` Nicolas Boichat
2019-03-08 6:20 ` Nicolas Boichat
2019-03-08 6:20 ` Nicolas Boichat
2019-04-11 20:14 ` Stephen Boyd
2019-04-11 20:14 ` Stephen Boyd
2019-04-11 20:14 ` Stephen Boyd
2019-04-11 20:16 ` Stephen Boyd
2019-04-11 20:16 ` Stephen Boyd
2019-04-11 20:16 ` Stephen Boyd
2019-03-05 5:05 ` [PATCH v5 4/9] dt-bindings: ARM: Mediatek: Document bindings for MT8183 Weiyi Lu
2019-03-05 5:05 ` Weiyi Lu
2019-03-05 5:05 ` Weiyi Lu
2019-03-05 5:05 ` [PATCH v5 5/9] clk: mediatek: Add dt-bindings for MT8183 clocks Weiyi Lu
2019-03-05 5:05 ` Weiyi Lu
2019-03-05 5:05 ` Weiyi Lu
2019-04-11 20:16 ` Stephen Boyd
2019-04-11 20:16 ` Stephen Boyd
2019-04-11 20:16 ` Stephen Boyd
2019-03-05 5:05 ` [PATCH v5 6/9] clk: mediatek: Add flags support for mtk_gate data Weiyi Lu
2019-03-05 5:05 ` Weiyi Lu
2019-03-05 5:05 ` Weiyi Lu
2019-03-05 6:47 ` James Liao
2019-03-05 6:47 ` James Liao
2019-03-05 6:47 ` James Liao
2019-03-08 6:20 ` Nicolas Boichat
2019-03-08 6:20 ` Nicolas Boichat
2019-03-08 6:20 ` Nicolas Boichat
2019-04-11 20:19 ` Stephen Boyd
2019-04-11 20:19 ` Stephen Boyd
2019-04-11 20:19 ` Stephen Boyd
2019-04-12 2:42 ` Weiyi Lu
2019-04-12 2:42 ` Weiyi Lu
2019-04-12 2:42 ` Weiyi Lu
2019-03-05 5:05 ` [PATCH v5 7/9] clk: mediatek: Add configurable pcw_chg_reg to mtk_pll_data Weiyi Lu
2019-03-05 5:05 ` Weiyi Lu
2019-03-05 5:05 ` Weiyi Lu
2019-03-05 6:47 ` James Liao
2019-03-05 6:47 ` James Liao
2019-03-05 6:47 ` James Liao
2019-03-08 6:23 ` Nicolas Boichat
2019-03-08 6:23 ` Nicolas Boichat
2019-03-08 6:23 ` Nicolas Boichat
2019-04-11 20:21 ` Stephen Boyd
2019-04-11 20:21 ` Stephen Boyd
2019-04-11 20:21 ` Stephen Boyd
2019-03-05 5:05 ` [PATCH v5 8/9] clk: mediatek: Add MT8183 clock support Weiyi Lu
2019-03-05 5:05 ` Weiyi Lu
2019-03-05 5:05 ` Weiyi Lu
2019-03-08 6:42 ` Nicolas Boichat
2019-03-08 6:42 ` Nicolas Boichat
2019-03-08 6:42 ` Nicolas Boichat
2019-03-08 14:46 ` Nicolas Boichat
2019-03-08 14:46 ` Nicolas Boichat
2019-03-08 14:46 ` Nicolas Boichat
2019-04-11 20:24 ` Stephen Boyd
2019-04-11 20:24 ` Stephen Boyd
2019-04-11 20:24 ` Stephen Boyd
2019-04-11 20:24 ` Stephen Boyd
2019-04-11 20:24 ` Stephen Boyd
2019-04-11 20:24 ` Stephen Boyd
2019-03-05 5:05 ` [PATCH v5 9/9] clk: mediatek: Allow changing PLL rate when it is off Weiyi Lu
2019-03-05 5:05 ` Weiyi Lu
2019-03-05 5:05 ` Weiyi Lu
2019-03-05 6:48 ` James Liao
2019-03-05 6:48 ` James Liao
2019-03-05 6:48 ` James Liao
2019-04-11 20:24 ` Stephen Boyd
2019-04-11 20:24 ` Stephen Boyd
2019-04-11 20:24 ` Stephen Boyd
2019-03-28 5:18 ` Weiyi Lu [this message]
2019-03-28 5:18 ` [PATCH v5 0/9] Mediatek MT8183 clock support Weiyi Lu
2019-03-28 5:18 ` Weiyi Lu
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