From: Matthias Brugger <matthias.bgg@gmail.com> To: Weiyi Lu <weiyi.lu@mediatek.com>, Nicolas Boichat <drinkcat@chromium.org>, Stephen Boyd <sboyd@codeaurora.org>, Rob Herring <robh@kernel.org> Cc: James Liao <jamesjj.liao@mediatek.com>, Fan Chen <fan.chen@mediatek.com>, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-clk@vger.kernel.org, srv_heupstream@mediatek.com, stable@vger.kernel.org, Owen Chen <owen.chen@mediatek.com> Subject: Re: [PATCH v5 1/9] clk: mediatek: Disable tuner_en before change PLL rate Date: Thu, 7 Mar 2019 17:09:23 +0100 [thread overview] Message-ID: <43f25b61-73ea-1083-7ab0-9e73a6d87b89@gmail.com> (raw) In-Reply-To: <20190305050546.23431-3-weiyi.lu@mediatek.com> On 05/03/2019 06:05, Weiyi Lu wrote: > From: Owen Chen <owen.chen@mediatek.com> > > PLLs with tuner_en bit, such as APLL1, need to disable > tuner_en before apply new frequency settings, or the new frequency > settings (pcw) will not be applied. > The tuner_en bit will be disabled during changing PLL rate > and be restored after new settings applied. > > Fixes: e2f744a82d725 (clk: mediatek: Add MT2712 clock support) > Cc: <stable@vger.kernel.org> > Signed-off-by: Owen Chen <owen.chen@mediatek.com> > Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> > --- > drivers/clk/mediatek/clk-pll.c | 48 ++++++++++++++++++++++++---------- > 1 file changed, 34 insertions(+), 14 deletions(-) > > diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c > index f54e4015b0b1..18842d660317 100644 > --- a/drivers/clk/mediatek/clk-pll.c > +++ b/drivers/clk/mediatek/clk-pll.c > @@ -88,6 +88,32 @@ static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin, > return ((unsigned long)vco + postdiv - 1) / postdiv; > } > > +static void __mtk_pll_tuner_enable(struct mtk_clk_pll *pll) > +{ > + u32 r; > + > + if (pll->tuner_en_addr) { > + r = readl(pll->tuner_en_addr) | BIT(pll->data->tuner_en_bit); > + writel(r, pll->tuner_en_addr); > + } else if (pll->tuner_addr) { > + r = readl(pll->tuner_addr) | AUDPLL_TUNER_EN; > + writel(r, pll->tuner_addr); > + } > +} > + > +static void __mtk_pll_tuner_disable(struct mtk_clk_pll *pll) > +{ > + u32 r; > + > + if (pll->tuner_en_addr) { > + r = readl(pll->tuner_en_addr) & ~BIT(pll->data->tuner_en_bit); > + writel(r, pll->tuner_en_addr); > + } else if (pll->tuner_addr) { > + r = readl(pll->tuner_addr) & ~AUDPLL_TUNER_EN; > + writel(r, pll->tuner_addr); > + } > +} > + > static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw, > int postdiv) > { > @@ -96,6 +122,9 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw, > > pll_en = readl(pll->base_addr + REG_CON0) & CON0_BASE_EN; > > + /* disable tuner */ > + __mtk_pll_tuner_disable(pll); > + > /* set postdiv */ > val = readl(pll->pd_addr); > val &= ~(POSTDIV_MASK << pll->data->pd_shift); > @@ -122,6 +151,9 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw, > if (pll->tuner_addr) > writel(con1 + 1, pll->tuner_addr); > > + /* restore tuner_en */ > + __mtk_pll_tuner_enable(pll); > + > if (pll_en) > udelay(20); > } > @@ -228,13 +260,7 @@ static int mtk_pll_prepare(struct clk_hw *hw) > r |= pll->data->en_mask; > writel(r, pll->base_addr + REG_CON0); > > - if (pll->tuner_en_addr) { > - r = readl(pll->tuner_en_addr) | BIT(pll->data->tuner_en_bit); > - writel(r, pll->tuner_en_addr); > - } else if (pll->tuner_addr) { > - r = readl(pll->tuner_addr) | AUDPLL_TUNER_EN; > - writel(r, pll->tuner_addr); > - } > + __mtk_pll_tuner_enable(pll); > > udelay(20); > > @@ -258,13 +284,7 @@ static void mtk_pll_unprepare(struct clk_hw *hw) > writel(r, pll->base_addr + REG_CON0); > } > > - if (pll->tuner_en_addr) { > - r = readl(pll->tuner_en_addr) & ~BIT(pll->data->tuner_en_bit); > - writel(r, pll->tuner_en_addr); > - } else if (pll->tuner_addr) { > - r = readl(pll->tuner_addr) & ~AUDPLL_TUNER_EN; > - writel(r, pll->tuner_addr); > - } > + __mtk_pll_tuner_disable(pll); > > r = readl(pll->base_addr + REG_CON0); > r &= ~CON0_BASE_EN; >
WARNING: multiple messages have this Message-ID (diff)
From: Matthias Brugger <matthias.bgg@gmail.com> To: Weiyi Lu <weiyi.lu@mediatek.com>, Nicolas Boichat <drinkcat@chromium.org>, Stephen Boyd <sboyd@codeaurora.org>, Rob Herring <robh@kernel.org> Cc: James Liao <jamesjj.liao@mediatek.com>, srv_heupstream@mediatek.com, linux-kernel@vger.kernel.org, stable@vger.kernel.org, Fan Chen <fan.chen@mediatek.com>, linux-mediatek@lists.infradead.org, Owen Chen <owen.chen@mediatek.com>, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v5 1/9] clk: mediatek: Disable tuner_en before change PLL rate Date: Thu, 7 Mar 2019 17:09:23 +0100 [thread overview] Message-ID: <43f25b61-73ea-1083-7ab0-9e73a6d87b89@gmail.com> (raw) In-Reply-To: <20190305050546.23431-3-weiyi.lu@mediatek.com> On 05/03/2019 06:05, Weiyi Lu wrote: > From: Owen Chen <owen.chen@mediatek.com> > > PLLs with tuner_en bit, such as APLL1, need to disable > tuner_en before apply new frequency settings, or the new frequency > settings (pcw) will not be applied. > The tuner_en bit will be disabled during changing PLL rate > and be restored after new settings applied. > > Fixes: e2f744a82d725 (clk: mediatek: Add MT2712 clock support) > Cc: <stable@vger.kernel.org> > Signed-off-by: Owen Chen <owen.chen@mediatek.com> > Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> > --- > drivers/clk/mediatek/clk-pll.c | 48 ++++++++++++++++++++++++---------- > 1 file changed, 34 insertions(+), 14 deletions(-) > > diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c > index f54e4015b0b1..18842d660317 100644 > --- a/drivers/clk/mediatek/clk-pll.c > +++ b/drivers/clk/mediatek/clk-pll.c > @@ -88,6 +88,32 @@ static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin, > return ((unsigned long)vco + postdiv - 1) / postdiv; > } > > +static void __mtk_pll_tuner_enable(struct mtk_clk_pll *pll) > +{ > + u32 r; > + > + if (pll->tuner_en_addr) { > + r = readl(pll->tuner_en_addr) | BIT(pll->data->tuner_en_bit); > + writel(r, pll->tuner_en_addr); > + } else if (pll->tuner_addr) { > + r = readl(pll->tuner_addr) | AUDPLL_TUNER_EN; > + writel(r, pll->tuner_addr); > + } > +} > + > +static void __mtk_pll_tuner_disable(struct mtk_clk_pll *pll) > +{ > + u32 r; > + > + if (pll->tuner_en_addr) { > + r = readl(pll->tuner_en_addr) & ~BIT(pll->data->tuner_en_bit); > + writel(r, pll->tuner_en_addr); > + } else if (pll->tuner_addr) { > + r = readl(pll->tuner_addr) & ~AUDPLL_TUNER_EN; > + writel(r, pll->tuner_addr); > + } > +} > + > static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw, > int postdiv) > { > @@ -96,6 +122,9 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw, > > pll_en = readl(pll->base_addr + REG_CON0) & CON0_BASE_EN; > > + /* disable tuner */ > + __mtk_pll_tuner_disable(pll); > + > /* set postdiv */ > val = readl(pll->pd_addr); > val &= ~(POSTDIV_MASK << pll->data->pd_shift); > @@ -122,6 +151,9 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw, > if (pll->tuner_addr) > writel(con1 + 1, pll->tuner_addr); > > + /* restore tuner_en */ > + __mtk_pll_tuner_enable(pll); > + > if (pll_en) > udelay(20); > } > @@ -228,13 +260,7 @@ static int mtk_pll_prepare(struct clk_hw *hw) > r |= pll->data->en_mask; > writel(r, pll->base_addr + REG_CON0); > > - if (pll->tuner_en_addr) { > - r = readl(pll->tuner_en_addr) | BIT(pll->data->tuner_en_bit); > - writel(r, pll->tuner_en_addr); > - } else if (pll->tuner_addr) { > - r = readl(pll->tuner_addr) | AUDPLL_TUNER_EN; > - writel(r, pll->tuner_addr); > - } > + __mtk_pll_tuner_enable(pll); > > udelay(20); > > @@ -258,13 +284,7 @@ static void mtk_pll_unprepare(struct clk_hw *hw) > writel(r, pll->base_addr + REG_CON0); > } > > - if (pll->tuner_en_addr) { > - r = readl(pll->tuner_en_addr) & ~BIT(pll->data->tuner_en_bit); > - writel(r, pll->tuner_en_addr); > - } else if (pll->tuner_addr) { > - r = readl(pll->tuner_addr) & ~AUDPLL_TUNER_EN; > - writel(r, pll->tuner_addr); > - } > + __mtk_pll_tuner_disable(pll); > > r = readl(pll->base_addr + REG_CON0); > r &= ~CON0_BASE_EN; > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2019-03-07 16:09 UTC|newest] Thread overview: 116+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-03-05 5:05 [PATCH v5 0/9] Mediatek MT8183 clock support Weiyi Lu 2019-03-05 5:05 ` Weiyi Lu 2019-03-05 5:05 ` Weiyi Lu 2019-03-05 5:05 ` Weiyi Lu 2019-03-05 5:05 ` Weiyi Lu 2019-03-05 5:05 ` Weiyi Lu 2019-03-05 18:41 ` Stephen Boyd 2019-03-05 18:41 ` Stephen Boyd 2019-03-05 18:41 ` Stephen Boyd 2019-03-05 5:05 ` [PATCH v5 1/9] clk: mediatek: Disable tuner_en before change PLL rate Weiyi Lu 2019-03-05 5:05 ` Weiyi Lu 2019-03-05 5:05 ` Weiyi Lu 2019-03-05 6:42 ` James Liao 2019-03-05 6:42 ` James Liao 2019-03-05 6:42 ` James Liao 2019-03-07 16:09 ` Matthias Brugger [this message] 2019-03-07 16:09 ` Matthias Brugger 2019-04-11 20:16 ` Stephen Boyd 2019-04-11 20:16 ` Stephen Boyd 2019-04-11 20:16 ` Stephen Boyd 2019-03-05 5:05 ` [PATCH v5 2/9] clk: mediatek: Add new clkmux register API Weiyi Lu 2019-03-05 5:05 ` Weiyi Lu 2019-03-05 5:05 ` Weiyi Lu 2019-03-05 6:43 ` James Liao 2019-03-05 6:43 ` James Liao 2019-03-05 6:43 ` James Liao 2019-03-08 6:17 ` Nicolas Boichat 2019-03-08 6:17 ` Nicolas Boichat 2019-03-08 6:17 ` Nicolas Boichat 2019-03-14 23:21 ` Nicolas Boichat 2019-03-14 23:21 ` Nicolas Boichat 2019-03-14 23:21 ` Nicolas Boichat 2019-04-11 20:12 ` Stephen Boyd 2019-04-11 20:12 ` Stephen Boyd 2019-04-11 20:12 ` Stephen Boyd 2019-04-11 20:16 ` Stephen Boyd 2019-04-11 20:16 ` Stephen Boyd 2019-04-11 20:16 ` Stephen Boyd 2019-03-05 5:05 ` [PATCH v5 3/9] clk: mediatek: Add configurable pcwibits and fmin to mtk_pll_data Weiyi Lu 2019-03-05 5:05 ` Weiyi Lu 2019-03-05 5:05 ` Weiyi Lu 2019-03-05 6:46 ` James Liao 2019-03-05 6:46 ` James Liao 2019-03-05 6:46 ` James Liao 2019-03-08 6:20 ` Nicolas Boichat 2019-03-08 6:20 ` Nicolas Boichat 2019-03-08 6:20 ` Nicolas Boichat 2019-04-11 20:14 ` Stephen Boyd 2019-04-11 20:14 ` Stephen Boyd 2019-04-11 20:14 ` Stephen Boyd 2019-04-11 20:16 ` Stephen Boyd 2019-04-11 20:16 ` Stephen Boyd 2019-04-11 20:16 ` Stephen Boyd 2019-03-05 5:05 ` [PATCH v5 4/9] dt-bindings: ARM: Mediatek: Document bindings for MT8183 Weiyi Lu 2019-03-05 5:05 ` Weiyi Lu 2019-03-05 5:05 ` Weiyi Lu 2019-03-05 5:05 ` [PATCH v5 5/9] clk: mediatek: Add dt-bindings for MT8183 clocks Weiyi Lu 2019-03-05 5:05 ` Weiyi Lu 2019-03-05 5:05 ` Weiyi Lu 2019-04-11 20:16 ` Stephen Boyd 2019-04-11 20:16 ` Stephen Boyd 2019-04-11 20:16 ` Stephen Boyd 2019-03-05 5:05 ` [PATCH v5 6/9] clk: mediatek: Add flags support for mtk_gate data Weiyi Lu 2019-03-05 5:05 ` Weiyi Lu 2019-03-05 5:05 ` Weiyi Lu 2019-03-05 6:47 ` James Liao 2019-03-05 6:47 ` James Liao 2019-03-05 6:47 ` James Liao 2019-03-08 6:20 ` Nicolas Boichat 2019-03-08 6:20 ` Nicolas Boichat 2019-03-08 6:20 ` Nicolas Boichat 2019-04-11 20:19 ` Stephen Boyd 2019-04-11 20:19 ` Stephen Boyd 2019-04-11 20:19 ` Stephen Boyd 2019-04-12 2:42 ` Weiyi Lu 2019-04-12 2:42 ` Weiyi Lu 2019-04-12 2:42 ` Weiyi Lu 2019-03-05 5:05 ` [PATCH v5 7/9] clk: mediatek: Add configurable pcw_chg_reg to mtk_pll_data Weiyi Lu 2019-03-05 5:05 ` Weiyi Lu 2019-03-05 5:05 ` Weiyi Lu 2019-03-05 6:47 ` James Liao 2019-03-05 6:47 ` James Liao 2019-03-05 6:47 ` James Liao 2019-03-08 6:23 ` Nicolas Boichat 2019-03-08 6:23 ` Nicolas Boichat 2019-03-08 6:23 ` Nicolas Boichat 2019-04-11 20:21 ` Stephen Boyd 2019-04-11 20:21 ` Stephen Boyd 2019-04-11 20:21 ` Stephen Boyd 2019-03-05 5:05 ` [PATCH v5 8/9] clk: mediatek: Add MT8183 clock support Weiyi Lu 2019-03-05 5:05 ` Weiyi Lu 2019-03-05 5:05 ` Weiyi Lu 2019-03-08 6:42 ` Nicolas Boichat 2019-03-08 6:42 ` Nicolas Boichat 2019-03-08 6:42 ` Nicolas Boichat 2019-03-08 14:46 ` Nicolas Boichat 2019-03-08 14:46 ` Nicolas Boichat 2019-03-08 14:46 ` Nicolas Boichat 2019-04-11 20:24 ` Stephen Boyd 2019-04-11 20:24 ` Stephen Boyd 2019-04-11 20:24 ` Stephen Boyd 2019-04-11 20:24 ` Stephen Boyd 2019-04-11 20:24 ` Stephen Boyd 2019-04-11 20:24 ` Stephen Boyd 2019-03-05 5:05 ` [PATCH v5 9/9] clk: mediatek: Allow changing PLL rate when it is off Weiyi Lu 2019-03-05 5:05 ` Weiyi Lu 2019-03-05 5:05 ` Weiyi Lu 2019-03-05 6:48 ` James Liao 2019-03-05 6:48 ` James Liao 2019-03-05 6:48 ` James Liao 2019-04-11 20:24 ` Stephen Boyd 2019-04-11 20:24 ` Stephen Boyd 2019-04-11 20:24 ` Stephen Boyd 2019-03-28 5:18 ` [PATCH v5 0/9] Mediatek MT8183 clock support Weiyi Lu 2019-03-28 5:18 ` Weiyi Lu 2019-03-28 5:18 ` Weiyi Lu
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