From: CK Hu <ck.hu@mediatek.com>
To: <yongqiang.niu@mediatek.com>
Cc: Philipp Zabel <p.zabel@pengutronix.de>,
Rob Herring <robh+dt@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
"David Airlie" <airlied@linux.ie>,
Daniel Vetter <daniel@ffwll.ch>,
Mark Rutland <mark.rutland@arm.com>,
<dri-devel@lists.freedesktop.org>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-mediatek@lists.infradead.org>
Subject: Re: [PATCH v4, 12/33] drm/mediatek: split DISP_REG_CONFIG_DSI_SEL setting into another use case
Date: Wed, 17 Jul 2019 13:35:36 +0800 [thread overview]
Message-ID: <1563341736.29169.15.camel@mtksdaap41> (raw)
In-Reply-To: <1562625253-29254-13-git-send-email-yongqiang.niu@mediatek.com>
Hi, Yongqiang:
On Tue, 2019-07-09 at 06:33 +0800, yongqiang.niu@mediatek.com wrote:
> From: Yongqiang Niu <yongqiang.niu@mediatek.com>
>
> Here is two modifition in this patch:
> 1.bls->dpi0 and rdma1->dsi are differen usecase,
> Split DISP_REG_CONFIG_DSI_SEL setting into anther usecase
> 2.remove DISP_REG_CONFIG_DPI_SEL setting, DPI_SEL_IN_BLS is 0 and
> this is same with hardware defautl setting,
>
You move 2 register setting out of the path from BLS to DPI0, does this
path still work? Please make sure that all modification could work on
all supported SoC.
Regards,
CK
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> index d015c1a..47b3e35 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> @@ -400,10 +400,9 @@ static void mtk_ddp_sout_sel(void __iomem *config_regs,
> } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) {
> writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI,
> config_regs + DISP_REG_CONFIG_OUT_SEL);
> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) {
> writel_relaxed(DSI_SEL_IN_RDMA,
> config_regs + DISP_REG_CONFIG_DSI_SEL);
> - writel_relaxed(DPI_SEL_IN_BLS,
> - config_regs + DISP_REG_CONFIG_DPI_SEL);
> }
> }
>
WARNING: multiple messages have this Message-ID (diff)
From: CK Hu <ck.hu@mediatek.com>
To: yongqiang.niu@mediatek.com
Cc: Mark Rutland <mark.rutland@arm.com>,
devicetree@vger.kernel.org,
Philipp Zabel <p.zabel@pengutronix.de>,
David Airlie <airlied@linux.ie>,
linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
Rob Herring <robh+dt@kernel.org>,
linux-mediatek@lists.infradead.org,
Daniel Vetter <daniel@ffwll.ch>,
Matthias Brugger <matthias.bgg@gmail.com>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v4, 12/33] drm/mediatek: split DISP_REG_CONFIG_DSI_SEL setting into another use case
Date: Wed, 17 Jul 2019 13:35:36 +0800 [thread overview]
Message-ID: <1563341736.29169.15.camel@mtksdaap41> (raw)
In-Reply-To: <1562625253-29254-13-git-send-email-yongqiang.niu@mediatek.com>
Hi, Yongqiang:
On Tue, 2019-07-09 at 06:33 +0800, yongqiang.niu@mediatek.com wrote:
> From: Yongqiang Niu <yongqiang.niu@mediatek.com>
>
> Here is two modifition in this patch:
> 1.bls->dpi0 and rdma1->dsi are differen usecase,
> Split DISP_REG_CONFIG_DSI_SEL setting into anther usecase
> 2.remove DISP_REG_CONFIG_DPI_SEL setting, DPI_SEL_IN_BLS is 0 and
> this is same with hardware defautl setting,
>
You move 2 register setting out of the path from BLS to DPI0, does this
path still work? Please make sure that all modification could work on
all supported SoC.
Regards,
CK
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> index d015c1a..47b3e35 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> @@ -400,10 +400,9 @@ static void mtk_ddp_sout_sel(void __iomem *config_regs,
> } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) {
> writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI,
> config_regs + DISP_REG_CONFIG_OUT_SEL);
> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) {
> writel_relaxed(DSI_SEL_IN_RDMA,
> config_regs + DISP_REG_CONFIG_DSI_SEL);
> - writel_relaxed(DPI_SEL_IN_BLS,
> - config_regs + DISP_REG_CONFIG_DPI_SEL);
> }
> }
>
WARNING: multiple messages have this Message-ID (diff)
From: CK Hu <ck.hu@mediatek.com>
To: <yongqiang.niu@mediatek.com>
Cc: Mark Rutland <mark.rutland@arm.com>,
devicetree@vger.kernel.org,
Philipp Zabel <p.zabel@pengutronix.de>,
David Airlie <airlied@linux.ie>,
linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
Rob Herring <robh+dt@kernel.org>,
linux-mediatek@lists.infradead.org,
Daniel Vetter <daniel@ffwll.ch>,
Matthias Brugger <matthias.bgg@gmail.com>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v4, 12/33] drm/mediatek: split DISP_REG_CONFIG_DSI_SEL setting into another use case
Date: Wed, 17 Jul 2019 13:35:36 +0800 [thread overview]
Message-ID: <1563341736.29169.15.camel@mtksdaap41> (raw)
In-Reply-To: <1562625253-29254-13-git-send-email-yongqiang.niu@mediatek.com>
Hi, Yongqiang:
On Tue, 2019-07-09 at 06:33 +0800, yongqiang.niu@mediatek.com wrote:
> From: Yongqiang Niu <yongqiang.niu@mediatek.com>
>
> Here is two modifition in this patch:
> 1.bls->dpi0 and rdma1->dsi are differen usecase,
> Split DISP_REG_CONFIG_DSI_SEL setting into anther usecase
> 2.remove DISP_REG_CONFIG_DPI_SEL setting, DPI_SEL_IN_BLS is 0 and
> this is same with hardware defautl setting,
>
You move 2 register setting out of the path from BLS to DPI0, does this
path still work? Please make sure that all modification could work on
all supported SoC.
Regards,
CK
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> index d015c1a..47b3e35 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> @@ -400,10 +400,9 @@ static void mtk_ddp_sout_sel(void __iomem *config_regs,
> } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) {
> writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI,
> config_regs + DISP_REG_CONFIG_OUT_SEL);
> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) {
> writel_relaxed(DSI_SEL_IN_RDMA,
> config_regs + DISP_REG_CONFIG_DSI_SEL);
> - writel_relaxed(DPI_SEL_IN_BLS,
> - config_regs + DISP_REG_CONFIG_DPI_SEL);
> }
> }
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2019-07-17 5:35 UTC|newest]
Thread overview: 166+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-08 22:33 [PATCH v4, 00/33] add drm support for MT8183 yongqiang.niu
2019-07-08 22:33 ` yongqiang.niu
2019-07-08 22:33 ` yongqiang.niu
2019-07-08 22:33 ` [PATCH v4, 01/33] dt-bindings: mediatek: add binding for mt8183 display yongqiang.niu
2019-07-08 22:33 ` yongqiang.niu
2019-07-08 22:33 ` yongqiang.niu
2019-07-17 3:22 ` CK Hu
2019-07-17 3:22 ` CK Hu
2019-07-17 3:22 ` CK Hu
2019-07-08 22:33 ` [PATCH v4, 02/33] dt-bindings: mediatek: add ovl_2l description " yongqiang.niu
2019-07-08 22:33 ` yongqiang.niu
2019-07-08 22:33 ` yongqiang.niu
2019-07-24 20:15 ` Rob Herring
2019-07-24 20:15 ` Rob Herring
2019-07-24 20:15 ` Rob Herring
2019-07-08 22:33 ` [PATCH v4, 03/33] dt-bindings: mediatek: add ccorr " yongqiang.niu
2019-07-08 22:33 ` yongqiang.niu
2019-07-08 22:33 ` yongqiang.niu-NuS5LvNUpcJWk0Htik3J/w
2019-07-17 3:37 ` CK Hu
2019-07-17 3:37 ` CK Hu
2019-07-17 3:37 ` CK Hu
2019-07-08 22:33 ` [PATCH v4, 04/33] dt-bindings: mediatek: add dither " yongqiang.niu
2019-07-08 22:33 ` yongqiang.niu
2019-07-08 22:33 ` yongqiang.niu-NuS5LvNUpcJWk0Htik3J/w
2019-07-17 3:40 ` CK Hu
2019-07-17 3:40 ` CK Hu
2019-07-17 3:40 ` CK Hu
2019-07-08 22:33 ` [PATCH v4, 05/33] dt-bindings: mediatek: add RDMA1 " yongqiang.niu
2019-07-08 22:33 ` yongqiang.niu
2019-07-08 22:33 ` yongqiang.niu
2019-07-24 20:16 ` Rob Herring
2019-07-24 20:16 ` Rob Herring
2019-07-24 20:16 ` Rob Herring
2019-07-25 3:20 ` CK Hu
2019-07-25 3:20 ` CK Hu
2019-07-25 3:20 ` CK Hu
2019-07-25 22:23 ` Rob Herring
2019-07-25 22:23 ` Rob Herring
2019-07-25 22:23 ` Rob Herring
2019-07-08 22:33 ` [PATCH v4, 06/33] dt-bindings: mediatek: add mutex " yongqiang.niu
2019-07-08 22:33 ` yongqiang.niu
2019-07-08 22:33 ` yongqiang.niu
2019-07-16 23:59 ` Ryan Case
2019-07-16 23:59 ` Ryan Case
2019-07-08 22:33 ` [PATCH v4, 07/33] arm64: dts: add display nodes for mt8183 yongqiang.niu
2019-07-08 22:33 ` yongqiang.niu
2019-07-08 22:33 ` yongqiang.niu
2019-07-08 22:33 ` [PATCH v4, 08/33] drm/mediatek: add mutex mod into ddp private data yongqiang.niu
2019-07-08 22:33 ` yongqiang.niu
2019-07-08 22:33 ` yongqiang.niu
2019-07-17 5:22 ` CK Hu
2019-07-17 5:22 ` CK Hu
2019-07-17 5:22 ` CK Hu
2019-07-08 22:33 ` [PATCH v4, 09/33] drm/mediatek: add mutex mod register offset " yongqiang.niu
2019-07-08 22:33 ` yongqiang.niu
2019-07-08 22:33 ` yongqiang.niu-NuS5LvNUpcJWk0Htik3J/w
2019-07-17 5:23 ` CK Hu
2019-07-17 5:23 ` CK Hu
2019-07-17 5:23 ` CK Hu
2019-07-08 22:33 ` [PATCH v4, 10/33] drm/mediatek: add mutex sof " yongqiang.niu
2019-07-08 22:33 ` yongqiang.niu
2019-07-08 22:33 ` yongqiang.niu
2019-07-17 5:28 ` CK Hu
2019-07-17 5:28 ` CK Hu
2019-07-17 5:28 ` CK Hu
2019-07-08 22:33 ` [PATCH v4, 11/33] drm/mediatek: add mutex sof register offset " yongqiang.niu
2019-07-08 22:33 ` yongqiang.niu
2019-07-08 22:33 ` yongqiang.niu
2019-07-17 5:31 ` CK Hu
2019-07-17 5:31 ` CK Hu
2019-07-17 5:31 ` CK Hu
2019-07-08 22:33 ` [PATCH v4, 12/33] drm/mediatek: split DISP_REG_CONFIG_DSI_SEL setting into another use case yongqiang.niu
2019-07-08 22:33 ` yongqiang.niu
2019-07-08 22:33 ` yongqiang.niu
2019-07-17 5:35 ` CK Hu [this message]
2019-07-17 5:35 ` CK Hu
2019-07-17 5:35 ` CK Hu
2019-08-29 12:39 ` Yongqiang Niu
2019-08-29 12:39 ` Yongqiang Niu
2019-08-29 12:39 ` Yongqiang Niu
2019-07-08 22:33 ` [PATCH v4, 13/33] drm/mediatek: add mmsys private data for ddp path config yongqiang.niu
2019-07-08 22:33 ` yongqiang.niu
2019-07-08 22:33 ` yongqiang.niu
2019-07-17 5:46 ` CK Hu
2019-07-17 5:46 ` CK Hu
2019-07-17 5:46 ` CK Hu
2019-07-08 22:33 ` [PATCH v4, 14/33] drm/mediatek: move rdma sout from mtk_ddp_mout_en into mtk_ddp_sout_sel yongqiang.niu
2019-07-08 22:33 ` yongqiang.niu
2019-07-08 22:33 ` yongqiang.niu
2019-07-08 22:33 ` [PATCH v4, 15/33] drm/mediatek: add ddp component CCORR yongqiang.niu
2019-07-08 22:33 ` yongqiang.niu
2019-07-08 22:33 ` yongqiang.niu
2019-07-08 22:33 ` [PATCH v4, 16/33] drm/mediatek: add commponent OVL_2L0 yongqiang.niu
2019-07-08 22:33 ` yongqiang.niu
2019-07-08 22:33 ` yongqiang.niu
2019-07-08 22:33 ` [PATCH v4, 17/33] drm/mediatek: add component OVL_2L1 yongqiang.niu
2019-07-08 22:33 ` yongqiang.niu
2019-07-08 22:33 ` yongqiang.niu
2019-07-08 22:33 ` [PATCH v4, 18/33] drm/mediatek: add component DITHER yongqiang.niu
2019-07-08 22:33 ` yongqiang.niu
2019-07-08 22:33 ` yongqiang.niu
2019-07-08 22:33 ` [PATCH v4, 19/33] drm/mediatek: add gmc_bits for ovl private data yongqiang.niu
2019-07-08 22:33 ` yongqiang.niu
2019-07-08 22:33 ` yongqiang.niu
2019-07-08 22:34 ` [PATCH v4, 20/33] drm/medaitek: add layer_nr " yongqiang.niu
2019-07-08 22:34 ` yongqiang.niu
2019-07-08 22:34 ` yongqiang.niu
2019-07-08 22:34 ` [PATCH v4, 21/33] drm/mediatek: add function to background color input select for ovl/ovl_2l direct link yongqiang.niu
2019-07-08 22:34 ` yongqiang.niu
2019-07-08 22:34 ` yongqiang.niu
2019-07-17 5:53 ` CK Hu
2019-07-17 5:53 ` CK Hu
2019-07-17 5:53 ` CK Hu
2019-07-08 22:34 ` [PATCH v4, 22/33] drm/mediatek: add background color input select function for ovl/ovl_2l yongqiang.niu
2019-07-08 22:34 ` yongqiang.niu
2019-07-08 22:34 ` yongqiang.niu
2019-07-17 5:58 ` CK Hu
2019-07-17 5:58 ` CK Hu
2019-07-17 5:58 ` CK Hu
2019-07-08 22:34 ` [PATCH v4, 23/33] drm/mediatek: add ovl0/ovl_2l0 usecase yongqiang.niu
2019-07-08 22:34 ` yongqiang.niu
2019-07-08 22:34 ` yongqiang.niu
2019-07-16 23:13 ` Ryan Case
2019-07-16 23:13 ` Ryan Case
2019-07-17 6:47 ` CK Hu
2019-07-17 6:47 ` CK Hu
2019-07-17 6:47 ` CK Hu
2019-08-29 13:15 ` Yongqiang Niu
2019-08-29 13:15 ` Yongqiang Niu
2019-08-29 13:15 ` Yongqiang Niu
2019-07-08 22:34 ` [PATCH v4, 24/33] drm/mediatek: distinguish ovl and ovl_2l by layer_nr yongqiang.niu
2019-07-08 22:34 ` yongqiang.niu
2019-07-08 22:34 ` yongqiang.niu
2019-07-17 6:55 ` CK Hu
2019-07-17 6:55 ` CK Hu
2019-07-17 6:55 ` CK Hu
2019-07-08 22:34 ` [PATCH v4, 25/33] drm/mediatek: add clock property check before get it yongqiang.niu
2019-07-08 22:34 ` yongqiang.niu
2019-07-08 22:34 ` yongqiang.niu
2019-07-17 7:01 ` CK Hu
2019-07-17 7:01 ` CK Hu
2019-07-17 7:01 ` CK Hu
2019-07-08 22:34 ` [PATCH v4, 26/33] drm/mediatek: add connection from OVL0 to OVL_2L0 yongqiang.niu
2019-07-08 22:34 ` yongqiang.niu
2019-07-08 22:34 ` yongqiang.niu
2019-07-08 22:34 ` [PATCH v4, 27/33] drm/mediatek: add connection from RDMA0 to COLOR0 yongqiang.niu
2019-07-08 22:34 ` yongqiang.niu
2019-07-08 22:34 ` yongqiang.niu
2019-07-08 22:34 ` [PATCH v4, 28/33] drm/mediatek: add connection from RDMA1 to DSI0 yongqiang.niu
2019-07-08 22:34 ` yongqiang.niu
2019-07-08 22:34 ` yongqiang.niu
2019-07-08 22:34 ` [PATCH v4, 29/33] drm/mediatek: add connection from OVL_2L0 to RDMA0 yongqiang.niu
2019-07-08 22:34 ` yongqiang.niu
2019-07-08 22:34 ` yongqiang.niu
2019-07-08 22:34 ` [PATCH v4, 30/33] drm/mediatek: add connection from OVL_2L1 to RDMA1 yongqiang.niu
2019-07-08 22:34 ` yongqiang.niu
2019-07-08 22:34 ` yongqiang.niu
2019-07-08 22:34 ` [PATCH v4, 31/33] drm/mediatek: add connection from DITHER0 to DSI0 yongqiang.niu
2019-07-08 22:34 ` yongqiang.niu
2019-07-08 22:34 ` yongqiang.niu
2019-07-08 22:34 ` [PATCH v4, 32/33] drm/mediatek: add connection from RDMA0 " yongqiang.niu
2019-07-08 22:34 ` yongqiang.niu
2019-07-08 22:34 ` yongqiang.niu
2019-07-08 22:34 ` [PATCH v4, 33/33] drm/mediatek: add support for mediatek SOC MT8183 yongqiang.niu
2019-07-08 22:34 ` yongqiang.niu
2019-07-08 22:34 ` yongqiang.niu
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