From: fabrizio.castro@bp.renesas.com (Fabrizio Castro)
To: cip-dev@lists.cip-project.org
Subject: [cip-dev] [PATCH/RFC 4.19.y-cip v2 34/51] pinctrl: sh-pfc: rcar-gen3: Rename RTS{0, 1, 3, 4}# pin function definitions
Date: Thu, 29 Aug 2019 18:02:39 +0100 [thread overview]
Message-ID: <1567098176-1242-35-git-send-email-fabrizio.castro@bp.renesas.com> (raw)
In-Reply-To: <1567098176-1242-1-git-send-email-fabrizio.castro@bp.renesas.com>
From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
commit 624a7a12cc0cc776c9c82347ffe5ddce7218eeca upstream.
According to the R-Car Gen3 Hardware Manual Errata for Rev 1.50 of
Feb 12, 2019, the RTS{0,1,3,4}_#/TANS pin names defined in the GPSR and
IPSR registers are renamed to RTS{0,1,3,4}_#.
This patch updates the pin control drivers to reflect this.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[geert: Update R-Car H3 ES1.x, V3M, V3H, and D3]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
[fab: dropped changes not related to the r8a77990]
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
drivers/pinctrl/sh-pfc/pfc-r8a77990.c | 36 +++++++++++++++++------------------
1 file changed, 18 insertions(+), 18 deletions(-)
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
index 4557070..df43e37 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
@@ -2,7 +2,7 @@
/*
* R8A77990 processor support - PFC hardware block.
*
- * Copyright (C) 2018 Renesas Electronics Corp.
+ * Copyright (C) 2018-2019 Renesas Electronics Corp.
*
* This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7796.c
*
@@ -165,7 +165,7 @@
#define GPSR5_7 F_(SCK2_A, IP12_7_4)
#define GPSR5_6 F_(TX1, IP12_3_0)
#define GPSR5_5 F_(RX1, IP11_31_28)
-#define GPSR5_4 F_(RTS0_N_TANS_A, IP11_23_20)
+#define GPSR5_4 F_(RTS0_N_A, IP11_23_20)
#define GPSR5_3 F_(CTS0_N_A, IP11_19_16)
#define GPSR5_2 F_(TX0_A, IP11_15_12)
#define GPSR5_1 F_(RX0_A, IP11_11_8)
@@ -219,7 +219,7 @@
#define IP3_3_0 FM(A1) FM(IRQ1) FM(PWM3_A) FM(DU_DOTCLKIN1) FM(VI5_DATA0_A) FM(DU_DISP_CDE) FM(SDA6_B) FM(IETX) FM(QCPV_QDE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_7_4 FM(A2) FM(IRQ2) FM(AVB_AVTP_PPS) FM(VI4_CLKENB) FM(VI5_DATA1_A) FM(DU_DISP) FM(SCL6_B) F_(0, 0) FM(QSTVB_QVE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_11_8 FM(A3) FM(CTS4_N_A) FM(PWM4_A) FM(VI4_DATA12) F_(0, 0) FM(DU_DOTCLKOUT0) FM(HTX3_D) FM(IECLK) FM(LCDOUT12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3_15_12 FM(A4) FM(RTS4_N_TANS_A) FM(MSIOF3_SYNC_B) FM(VI4_DATA8) FM(PWM2_B) FM(DU_DG4) FM(RIF2_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3_15_12 FM(A4) FM(RTS4_N_A) FM(MSIOF3_SYNC_B) FM(VI4_DATA8) FM(PWM2_B) FM(DU_DG4) FM(RIF2_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_19_16 FM(A5) FM(SCK4_A) FM(MSIOF3_SCK_B) FM(VI4_DATA9) FM(PWM3_B) F_(0, 0) FM(RIF2_SYNC_B) F_(0, 0) FM(QPOLA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_23_20 FM(A6) FM(RX4_A) FM(MSIOF3_RXD_B) FM(VI4_DATA10) F_(0, 0) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_27_24 FM(A7) FM(TX4_A) FM(MSIOF3_TXD_B) FM(VI4_DATA11) F_(0, 0) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -240,10 +240,10 @@
#define IP5_15_12 FM(CS0_N) FM(SCL5) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR0) FM(VI4_DATA2_B) F_(0, 0) FM(LCDOUT16) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP5_19_16 FM(WE0_N) FM(SDA5) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR1) FM(VI4_DATA3_B) F_(0, 0) FM(LCDOUT17) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP5_23_20 FM(D0) FM(MSIOF3_SCK_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR2) FM(CTS4_N_C) F_(0, 0) FM(LCDOUT18) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP5_27_24 FM(D1) FM(MSIOF3_SYNC_A) FM(SCK3_A) FM(VI4_DATA23) FM(VI5_CLKENB_A) FM(DU_DB7) FM(RTS4_N_TANS_C) F_(0, 0) FM(LCDOUT7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP5_27_24 FM(D1) FM(MSIOF3_SYNC_A) FM(SCK3_A) FM(VI4_DATA23) FM(VI5_CLKENB_A) FM(DU_DB7) FM(RTS4_N_C) F_(0, 0) FM(LCDOUT7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP5_31_28 FM(D2) FM(MSIOF3_RXD_A) FM(RX5_C) F_(0, 0) FM(VI5_DATA14_A) FM(DU_DR3) FM(RX4_C) F_(0, 0) FM(LCDOUT19) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP6_3_0 FM(D3) FM(MSIOF3_TXD_A) FM(TX5_C) F_(0, 0) FM(VI5_DATA15_A) FM(DU_DR4) FM(TX4_C) F_(0, 0) FM(LCDOUT20) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_7_4 FM(D4) FM(CANFD1_TX) FM(HSCK3_B) FM(CAN1_TX) FM(RTS3_N_TANS_A) FM(MSIOF3_SS2_A) F_(0, 0) FM(VI5_DATA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_7_4 FM(D4) FM(CANFD1_TX) FM(HSCK3_B) FM(CAN1_TX) FM(RTS3_N_A) FM(MSIOF3_SS2_A) F_(0, 0) FM(VI5_DATA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP6_11_8 FM(D5) FM(RX3_A) FM(HRX3_B) F_(0, 0) F_(0, 0) FM(DU_DR5) FM(VI4_DATA4_B) F_(0, 0) FM(LCDOUT21) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP6_15_12 FM(D6) FM(TX3_A) FM(HTX3_B) F_(0, 0) F_(0, 0) FM(DU_DR6) FM(VI4_DATA5_B) F_(0, 0) FM(LCDOUT22) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP6_19_16 FM(D7) FM(CANFD1_RX) FM(IRQ5) FM(CAN1_RX) FM(CTS3_N_A) F_(0, 0) F_(0, 0) FM(VI5_DATA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -289,8 +289,8 @@
#define IP11_11_8 FM(RX0_A) FM(HRX1_A) FM(SSI_SCK2_A) FM(RIF1_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP11_15_12 FM(TX0_A) FM(HTX1_A) FM(SSI_WS2_A) FM(RIF1_D0) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP11_19_16 FM(CTS0_N_A) FM(NFDATA14_A) FM(AUDIO_CLKOUT_A) FM(RIF1_D1) FM(SCIF_CLK_A) FM(FMCLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP11_23_20 FM(RTS0_N_TANS_A) FM(NFDATA15_A) FM(AUDIO_CLKOUT1_A) FM(RIF1_CLK) FM(SCL2_A) FM(FMIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP11_27_24 FM(SCK0_A) FM(HSCK1_A) FM(USB3HS0_ID) FM(RTS1_N_TANS) FM(SDA2_A) FM(FMCLK_C) F_(0, 0) F_(0, 0) FM(USB0_ID) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP11_23_20 FM(RTS0_N_A) FM(NFDATA15_A) FM(AUDIO_CLKOUT1_A) FM(RIF1_CLK) FM(SCL2_A) FM(FMIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP11_27_24 FM(SCK0_A) FM(HSCK1_A) FM(USB3HS0_ID) FM(RTS1_N) FM(SDA2_A) FM(FMCLK_C) F_(0, 0) F_(0, 0) FM(USB0_ID) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP11_31_28 FM(RX1) FM(HRX2_B) FM(SSI_SCK9_B) FM(AUDIO_CLKOUT1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 - F */
@@ -668,7 +668,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP3_11_8, LCDOUT12),
PINMUX_IPSR_GPSR(IP3_15_12, A4),
- PINMUX_IPSR_MSEL(IP3_15_12, RTS4_N_TANS_A, SEL_SCIF4_0),
+ PINMUX_IPSR_MSEL(IP3_15_12, RTS4_N_A, SEL_SCIF4_0),
PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SYNC_B, SEL_MSIOF3_1),
PINMUX_IPSR_GPSR(IP3_15_12, VI4_DATA8),
PINMUX_IPSR_MSEL(IP3_15_12, PWM2_B, SEL_PWM2_1),
@@ -818,7 +818,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA23),
PINMUX_IPSR_MSEL(IP5_27_24, VI5_CLKENB_A, SEL_VIN5_0),
PINMUX_IPSR_GPSR(IP5_27_24, DU_DB7),
- PINMUX_IPSR_MSEL(IP5_27_24, RTS4_N_TANS_C, SEL_SCIF4_2),
+ PINMUX_IPSR_MSEL(IP5_27_24, RTS4_N_C, SEL_SCIF4_2),
PINMUX_IPSR_GPSR(IP5_27_24, LCDOUT7),
PINMUX_IPSR_GPSR(IP5_31_28, D2),
@@ -842,7 +842,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP6_7_4, CANFD1_TX),
PINMUX_IPSR_MSEL(IP6_7_4, HSCK3_B, SEL_HSCIF3_1),
PINMUX_IPSR_GPSR(IP6_7_4, CAN1_TX),
- PINMUX_IPSR_MSEL(IP6_7_4, RTS3_N_TANS_A, SEL_SCIF3_0),
+ PINMUX_IPSR_MSEL(IP6_7_4, RTS3_N_A, SEL_SCIF3_0),
PINMUX_IPSR_GPSR(IP6_7_4, MSIOF3_SS2_A),
PINMUX_IPSR_MSEL(IP6_7_4, VI5_DATA1_B, SEL_VIN5_1),
@@ -1083,7 +1083,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP11_19_16, SCIF_CLK_A, SEL_SCIF_0),
PINMUX_IPSR_MSEL(IP11_19_16, FMCLK_A, SEL_FM_0),
- PINMUX_IPSR_MSEL(IP11_23_20, RTS0_N_TANS_A, SEL_SCIF0_0),
+ PINMUX_IPSR_MSEL(IP11_23_20, RTS0_N_A, SEL_SCIF0_0),
PINMUX_IPSR_MSEL(IP11_23_20, NFDATA15_A, SEL_NDFC_0),
PINMUX_IPSR_GPSR(IP11_23_20, AUDIO_CLKOUT1_A),
PINMUX_IPSR_GPSR(IP11_23_20, RIF1_CLK),
@@ -1093,7 +1093,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP11_27_24, SCK0_A, SEL_SCIF0_0),
PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_A, SEL_HSCIF1_0),
PINMUX_IPSR_GPSR(IP11_27_24, USB3HS0_ID),
- PINMUX_IPSR_GPSR(IP11_27_24, RTS1_N_TANS),
+ PINMUX_IPSR_GPSR(IP11_27_24, RTS1_N),
PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
PINMUX_IPSR_MSEL(IP11_27_24, FMCLK_C, SEL_FM_2),
PINMUX_IPSR_GPSR(IP11_27_24, USB0_ID),
@@ -2836,7 +2836,7 @@ static const unsigned int scif0_ctrl_a_pins[] = {
};
static const unsigned int scif0_ctrl_a_mux[] = {
- RTS0_N_TANS_A_MARK, CTS0_N_A_MARK,
+ RTS0_N_A_MARK, CTS0_N_A_MARK,
};
static const unsigned int scif0_data_b_pins[] = {
@@ -2882,7 +2882,7 @@ static const unsigned int scif1_ctrl_pins[] = {
};
static const unsigned int scif1_ctrl_mux[] = {
- RTS1_N_TANS_MARK, CTS1_N_MARK,
+ RTS1_N_MARK, CTS1_N_MARK,
};
/* - SCIF2 ------------------------------------------------------------------ */
@@ -2938,7 +2938,7 @@ static const unsigned int scif3_ctrl_a_pins[] = {
};
static const unsigned int scif3_ctrl_a_mux[] = {
- RTS3_N_TANS_A_MARK, CTS3_N_A_MARK,
+ RTS3_N_A_MARK, CTS3_N_A_MARK,
};
static const unsigned int scif3_data_b_pins[] = {
@@ -2993,7 +2993,7 @@ static const unsigned int scif4_ctrl_a_pins[] = {
};
static const unsigned int scif4_ctrl_a_mux[] = {
- RTS4_N_TANS_A_MARK, CTS4_N_A_MARK,
+ RTS4_N_A_MARK, CTS4_N_A_MARK,
};
static const unsigned int scif4_data_b_pins[] = {
@@ -3029,7 +3029,7 @@ static const unsigned int scif4_ctrl_c_pins[] = {
};
static const unsigned int scif4_ctrl_c_mux[] = {
- RTS4_N_TANS_C_MARK, CTS4_N_C_MARK,
+ RTS4_N_C_MARK, CTS4_N_C_MARK,
};
/* - SCIF5 ------------------------------------------------------------------ */
@@ -5125,7 +5125,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
} },
{ PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
[0] = RCAR_GP_PIN(5, 0), /* SCK0_A */
- [1] = RCAR_GP_PIN(5, 4), /* RTS0#/TANS_A */
+ [1] = RCAR_GP_PIN(5, 4), /* RTS0#_A */
[2] = RCAR_GP_PIN(5, 3), /* CTS0#_A */
[3] = RCAR_GP_PIN(5, 2), /* TX0_A */
[4] = RCAR_GP_PIN(5, 1), /* RX0_A */
--
2.7.4
next prev parent reply other threads:[~2019-08-29 17:02 UTC|newest]
Thread overview: 53+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-29 17:02 [cip-dev] [PATCH/RFC 4.19.y-cip v2 00/51] Fast forward sh-pfc Fabrizio Castro
2019-08-29 17:02 ` [cip-dev] [PATCH/RFC 4.19.y-cip v2 01/51] pinctrl: sh-pfc: Print actual field width for variable-width fields Fabrizio Castro
2019-08-29 17:02 ` [cip-dev] [PATCH/RFC 4.19.y-cip v2 02/51] pinctrl: sh-pfc: Validate pinmux tables at runtime when debugging Fabrizio Castro
2019-08-29 17:02 ` [cip-dev] [PATCH/RFC 4.19.y-cip v2 03/51] pinctrl: sh-pfc: Add physical pin multiplexing helper macros Fabrizio Castro
2019-08-29 17:02 ` [cip-dev] [PATCH/RFC 4.19.y-cip v2 04/51] pinctrl: sh-pfc: Validate pins/marks in pin groups at build time Fabrizio Castro
2019-08-29 17:02 ` [cip-dev] [PATCH/RFC 4.19.y-cip v2 05/51] pinctrl: sh-pfc: Make pinmux_cfg_reg.var_field_width[] variable-length Fabrizio Castro
2019-08-29 17:02 ` [cip-dev] [PATCH/RFC 4.19.y-cip v2 06/51] pinctrl: sh-pfc: Validate fixed-size field widths at build time Fabrizio Castro
2019-08-29 17:02 ` [cip-dev] [PATCH/RFC 4.19.y-cip v2 07/51] pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG() macro Fabrizio Castro
2019-08-29 17:02 ` [cip-dev] [PATCH/RFC 4.19.y-cip v2 08/51] pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG_VAR() macro Fabrizio Castro
2019-08-29 17:02 ` [cip-dev] [PATCH/RFC 4.19.y-cip v2 09/51] pinctrl: sh-pfc: Absorb enum IDs in PINMUX_DATA_REG() macro Fabrizio Castro
2019-08-29 17:02 ` [cip-dev] [PATCH/RFC 4.19.y-cip v2 10/51] pinctrl: sh-pfc: Validate enum IDs for regs with fixed-width fields Fabrizio Castro
2019-08-29 17:02 ` [cip-dev] [PATCH/RFC 4.19.y-cip v2 11/51] pinctrl: sh-pfc: Validate enum IDs for regs with variable-width fields Fabrizio Castro
2019-08-29 17:02 ` [cip-dev] [PATCH/RFC 4.19.y-cip v2 12/51] pinctrl: sh-pfc: Improve PINMUX_IPSR_PHYS() documentation Fabrizio Castro
2019-08-29 17:02 ` [cip-dev] [PATCH/RFC 4.19.y-cip v2 13/51] pinctrl: sh-pfc: Rename 2-parameter CPU_ALL_PORT() variant Fabrizio Castro
2019-08-29 17:02 ` [cip-dev] [PATCH/RFC 4.19.y-cip v2 14/51] pinctrl: sh-pfc: Add SH_PFC_PIN_CFG_PULL_UP_DOWN shorthand Fabrizio Castro
2019-08-29 17:02 ` [cip-dev] [PATCH/RFC 4.19.y-cip v2 15/51] pinctrl: sh-pfc: Add new non-GPIO helper macros Fabrizio Castro
2019-08-29 17:02 ` [cip-dev] [PATCH/RFC 4.19.y-cip v2 16/51] pinctrl: sh-pfc: Correct printk level of group reference warning Fabrizio Castro
2019-08-29 17:02 ` [cip-dev] [PATCH/RFC 4.19.y-cip v2 17/51] pinctrl: sh-pfc: Mark run-time debug code __init Fabrizio Castro
2019-08-29 17:02 ` [cip-dev] [PATCH/RFC 4.19.y-cip v2 18/51] pinctrl: sh-pfc: Add check for empty pinmux groups/functions Fabrizio Castro
2019-08-29 17:02 ` [cip-dev] [PATCH/RFC 4.19.y-cip v2 19/51] pinctrl: sh-pfc: Validate pin tables at runtime Fabrizio Castro
2019-08-29 17:02 ` [cip-dev] [PATCH/RFC 4.19.y-cip v2 20/51] pinctrl: sh-pfc: r8a7796: Fix VIN versioned groups Fabrizio Castro
2019-08-29 17:02 ` [cip-dev] [PATCH/RFC 4.19.y-cip v2 21/51] pinctrl: sh-pfc: r8a7796: Add I2C{0, 3, 5} pins, groups and functions Fabrizio Castro
2019-08-29 17:02 ` [cip-dev] [PATCH/RFC 4.19.y-cip v2 22/51] pinctrl: sh-pfc: r8a7796: Deduplicate VIN5 pin definitions Fabrizio Castro
2019-08-29 17:02 ` [cip-dev] [PATCH/RFC 4.19.y-cip v2 23/51] pinctrl: sh-pfc: r8a7796: Move CANFD pin groups and functions Fabrizio Castro
2019-08-29 17:02 ` [cip-dev] [PATCH/RFC 4.19.y-cip v2 24/51] pinctrl: sh-pfc: r8a77990: Rename IOCTRLx registers Fabrizio Castro
2019-08-29 17:02 ` [cip-dev] [PATCH/RFC 4.19.y-cip v2 25/51] pinctrl: sh-pfc: r8a77990: Move CANFD pin groups and functions Fabrizio Castro
2019-08-29 17:02 ` [cip-dev] [PATCH/RFC 4.19.y-cip v2 26/51] pinctrl: sh-pfc: rcar-gen3: Retain TDSELCTRL register across suspend/resume Fabrizio Castro
2019-08-29 17:02 ` [cip-dev] [PATCH/RFC 4.19.y-cip v2 27/51] pinctrl: sh-pfc: Add missing #include <linux/errno.h> Fabrizio Castro
2019-08-29 17:02 ` [cip-dev] [PATCH/RFC 4.19.y-cip v2 28/51] pinctrl: sh-pfc: rcar-gen3: Remove HDMI CEC pins, groups, and functions Fabrizio Castro
2019-08-29 17:02 ` [cip-dev] [PATCH/RFC 4.19.y-cip v2 29/51] pinctrl: sh-pfc: rcar-gen3: Remove CC5_OSCOUT pin Fabrizio Castro
2019-08-29 17:02 ` [cip-dev] [PATCH/RFC 4.19.y-cip v2 30/51] pinctrl: sh-pfc: rcar-gen3: Rename SEL_ADG_{A, B, C} to SEL_ADG{A, B, C} Fabrizio Castro
2019-08-29 17:02 ` [cip-dev] [PATCH/RFC 4.19.y-cip v2 31/51] pinctrl: sh-pfc: r8a77990: Fix MOD_SEL0 bit16 when using NFALE and NFRB_N Fabrizio Castro
2019-08-29 17:02 ` [cip-dev] [PATCH/RFC 4.19.y-cip v2 32/51] pinctrl: sh-pfc: r8a77990: Fix MOD_SEL1 bit31 when using SIM0_D Fabrizio Castro
2019-08-29 17:02 ` [cip-dev] [PATCH/RFC 4.19.y-cip v2 33/51] pinctrl: sh-pfc: r8a77990: Fix MOD_SEL1 bit30 when using SSI_SCK2 and SSI_WS2 Fabrizio Castro
2019-08-29 17:02 ` Fabrizio Castro [this message]
2019-08-29 17:02 ` [cip-dev] [PATCH/RFC 4.19.y-cip v2 35/51] pinctrl: sh-pfc: rcar-gen3: Rename SEL_NDFC to SEL_NDF Fabrizio Castro
2019-08-29 17:02 ` [cip-dev] [PATCH/RFC 4.19.y-cip v2 36/51] pinctrl: sh-pfc: Add PORT_GP_27 helper macro Fabrizio Castro
2019-08-29 17:02 ` [cip-dev] [PATCH/RFC 4.19.y-cip v2 37/51] pinctrl: sh-pfc: Move PIN_NONE to shared header file Fabrizio Castro
2019-08-29 17:02 ` [cip-dev] [PATCH/RFC 4.19.y-cip v2 38/51] pinctrl: sh-pfc: r8a77990: Use new macros for non-GPIO pins Fabrizio Castro
2019-08-29 17:02 ` [cip-dev] [PATCH/RFC 4.19.y-cip v2 39/51] pinctrl: sh-pfc: r8a7796: Add TPU pins, groups and functions Fabrizio Castro
2019-08-29 17:02 ` [cip-dev] [PATCH/RFC 4.19.y-cip v2 40/51] pinctrl: sh-pfc: r8a7796: Use new macros for non-GPIO pins Fabrizio Castro
2019-08-29 17:02 ` [cip-dev] [PATCH/RFC 4.19.y-cip v2 41/51] pinctrl: sh-pfc: r8a7796: Remove placeholder I2C pin data Fabrizio Castro
2019-08-29 17:02 ` [cip-dev] [PATCH/RFC 4.19.y-cip v2 42/51] pinctrl: sh-pfc: r8a77995: Remove unused PINMUX_IPSR_{MSEL2, PHYS}() Fabrizio Castro
2019-08-29 17:02 ` [cip-dev] [PATCH/RFC 4.19.y-cip v2 43/51] pinctrl: sh-pfc: r8a7740: Add missing REF125CK pin to gether_gmii group Fabrizio Castro
2019-08-29 17:02 ` [cip-dev] [PATCH/RFC 4.19.y-cip v2 44/51] pinctrl: sh-pfc: r8a7740: Add missing LCD0 marks to lcd0_data24_1 group Fabrizio Castro
2019-08-29 17:02 ` [cip-dev] [PATCH/RFC 4.19.y-cip v2 45/51] pinctrl: sh-pfc: r8a7791: Remove bogus ctrl marks from qspi_data4_b group Fabrizio Castro
2019-08-29 17:02 ` [cip-dev] [PATCH/RFC 4.19.y-cip v2 46/51] pinctrl: sh-pfc: r8a7791: Remove bogus marks from vin1_b_data18 group Fabrizio Castro
2019-08-29 17:02 ` [cip-dev] [PATCH/RFC 4.19.y-cip v2 47/51] pinctrl: sh-pfc: r8a7791: Fix VIN1 versioned groups Fabrizio Castro
2019-08-29 17:02 ` [cip-dev] [PATCH/RFC 4.19.y-cip v2 48/51] pinctrl: sh-pfc: r8a7791: Fix scifb2_data_c pin group Fabrizio Castro
2019-08-29 17:02 ` [cip-dev] [PATCH/RFC 4.19.y-cip v2 49/51] pinctrl: sh-pfc: sh73a0: Fix fsic_spdif pin groups Fabrizio Castro
2019-08-29 17:02 ` [cip-dev] [PATCH/RFC 4.19.y-cip v2 50/51] pinctrl: sh-pfc: sh73a0: Add missing TO pin to tpu4_to3 group Fabrizio Castro
2019-08-29 17:02 ` [cip-dev] [PATCH/RFC 4.19.y-cip v2 51/51] pinctrl: sh-pfc: sh73a0: Use new macros for non-GPIO pins Fabrizio Castro
2019-08-29 22:31 ` [cip-dev] [PATCH/RFC 4.19.y-cip v2 00/51] Fast forward sh-pfc Pavel Machek
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