From: CK Hu <ck.hu@mediatek.com>
To: <yongqiang.niu@mediatek.com>
Cc: Philipp Zabel <p.zabel@pengutronix.de>,
Rob Herring <robh+dt@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
"David Airlie" <airlied@linux.ie>,
Daniel Vetter <daniel@ffwll.ch>,
Mark Rutland <mark.rutland@arm.com>,
<dri-devel@lists.freedesktop.org>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-mediatek@lists.infradead.org>
Subject: Re: [PATCH v5, 21/32] drm/mediatek: add background color input select function for ovl/ovl_2l
Date: Wed, 9 Oct 2019 17:24:40 +0800 [thread overview]
Message-ID: <1570613080.7713.6.camel@mtksdaap41> (raw)
In-Reply-To: <1567090254-15566-22-git-send-email-yongqiang.niu@mediatek.com>
Hi, Yongqiang:
On Thu, 2019-08-29 at 22:50 +0800, yongqiang.niu@mediatek.com wrote:
> From: Yongqiang Niu <yongqiang.niu@mediatek.com>
>
> This patch add background color input select function for ovl/ovl_2l
>
> ovl include 4 DRAM layer and 1 background color layer
> ovl_2l include 4 DRAM layer and 1 background color layer
> DRAM layer frame buffer data from render hardware, GPU for example.
> backgournd color layer is embed in ovl/ovl_2l, we can only set
> it color, but not support DRAM frame buffer.
>
> for ovl0->ovl0_2l direct link usecase,
> we need set ovl0_2l background color intput select from ovl0
> if render send DRAM buffer layer number <=4, all these layer read
> by ovl.
> layer0 is at the bottom of all layers.
> layer3 is at the top of all layers.
> if render send DRAM buffer layer numbfer >=4 && <=6
> ovl0 read layer0~3
> ovl0_2l read layer4~5
> layer5 is at the top ot all these layers.
>
> the decision of how to setting ovl0/ovl0_2l read these layer data
> is controlled in mtk crtc, which will be another patch
>
Applied to mediatek-drm-next-5.5 [1], thanks.
[1]
https://github.com/ckhu-mediatek/linux.git-tags/commits/mediatek-drm-next-5.5
Regards,
CK
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> Reviewed-by: CK Hu <ck.hu@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 22 ++++++++++++++++++++++
> 1 file changed, 22 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> index baef066..eb3bf85 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> @@ -19,6 +19,8 @@
> #define DISP_REG_OVL_EN 0x000c
> #define DISP_REG_OVL_RST 0x0014
> #define DISP_REG_OVL_ROI_SIZE 0x0020
> +#define DISP_REG_OVL_DATAPATH_CON 0x0024
> +#define OVL_BGCLR_SEL_IN BIT(2)
> #define DISP_REG_OVL_ROI_BGCLR 0x0028
> #define DISP_REG_OVL_SRC_CON 0x002c
> #define DISP_REG_OVL_CON(n) (0x0030 + 0x20 * (n))
> @@ -237,6 +239,24 @@ static void mtk_ovl_layer_config(struct mtk_ddp_comp *comp, unsigned int idx,
> mtk_ovl_layer_on(comp, idx);
> }
>
> +static void mtk_ovl_bgclr_in_on(struct mtk_ddp_comp *comp)
> +{
> + unsigned int reg;
> +
> + reg = readl(comp->regs + DISP_REG_OVL_DATAPATH_CON);
> + reg = reg | OVL_BGCLR_SEL_IN;
> + writel(reg, comp->regs + DISP_REG_OVL_DATAPATH_CON);
> +}
> +
> +static void mtk_ovl_bgclr_in_off(struct mtk_ddp_comp *comp)
> +{
> + unsigned int reg;
> +
> + reg = readl(comp->regs + DISP_REG_OVL_DATAPATH_CON);
> + reg = reg & ~OVL_BGCLR_SEL_IN;
> + writel(reg, comp->regs + DISP_REG_OVL_DATAPATH_CON);
> +}
> +
> static const struct mtk_ddp_comp_funcs mtk_disp_ovl_funcs = {
> .config = mtk_ovl_config,
> .start = mtk_ovl_start,
> @@ -247,6 +267,8 @@ static void mtk_ovl_layer_config(struct mtk_ddp_comp *comp, unsigned int idx,
> .layer_on = mtk_ovl_layer_on,
> .layer_off = mtk_ovl_layer_off,
> .layer_config = mtk_ovl_layer_config,
> + .bgclr_in_on = mtk_ovl_bgclr_in_on,
> + .bgclr_in_off = mtk_ovl_bgclr_in_off,
> };
>
> static int mtk_disp_ovl_bind(struct device *dev, struct device *master,
WARNING: multiple messages have this Message-ID (diff)
From: CK Hu <ck.hu@mediatek.com>
To: yongqiang.niu@mediatek.com
Cc: Philipp Zabel <p.zabel@pengutronix.de>,
Rob Herring <robh+dt@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>,
Mark Rutland <mark.rutland@arm.com>,
dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org
Subject: Re: [PATCH v5, 21/32] drm/mediatek: add background color input select function for ovl/ovl_2l
Date: Wed, 9 Oct 2019 17:24:40 +0800 [thread overview]
Message-ID: <1570613080.7713.6.camel@mtksdaap41> (raw)
In-Reply-To: <1567090254-15566-22-git-send-email-yongqiang.niu@mediatek.com>
Hi, Yongqiang:
On Thu, 2019-08-29 at 22:50 +0800, yongqiang.niu@mediatek.com wrote:
> From: Yongqiang Niu <yongqiang.niu@mediatek.com>
>
> This patch add background color input select function for ovl/ovl_2l
>
> ovl include 4 DRAM layer and 1 background color layer
> ovl_2l include 4 DRAM layer and 1 background color layer
> DRAM layer frame buffer data from render hardware, GPU for example.
> backgournd color layer is embed in ovl/ovl_2l, we can only set
> it color, but not support DRAM frame buffer.
>
> for ovl0->ovl0_2l direct link usecase,
> we need set ovl0_2l background color intput select from ovl0
> if render send DRAM buffer layer number <=4, all these layer read
> by ovl.
> layer0 is at the bottom of all layers.
> layer3 is at the top of all layers.
> if render send DRAM buffer layer numbfer >=4 && <=6
> ovl0 read layer0~3
> ovl0_2l read layer4~5
> layer5 is at the top ot all these layers.
>
> the decision of how to setting ovl0/ovl0_2l read these layer data
> is controlled in mtk crtc, which will be another patch
>
Applied to mediatek-drm-next-5.5 [1], thanks.
[1]
https://github.com/ckhu-mediatek/linux.git-tags/commits/mediatek-drm-next-5.5
Regards,
CK
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> Reviewed-by: CK Hu <ck.hu@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 22 ++++++++++++++++++++++
> 1 file changed, 22 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> index baef066..eb3bf85 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> @@ -19,6 +19,8 @@
> #define DISP_REG_OVL_EN 0x000c
> #define DISP_REG_OVL_RST 0x0014
> #define DISP_REG_OVL_ROI_SIZE 0x0020
> +#define DISP_REG_OVL_DATAPATH_CON 0x0024
> +#define OVL_BGCLR_SEL_IN BIT(2)
> #define DISP_REG_OVL_ROI_BGCLR 0x0028
> #define DISP_REG_OVL_SRC_CON 0x002c
> #define DISP_REG_OVL_CON(n) (0x0030 + 0x20 * (n))
> @@ -237,6 +239,24 @@ static void mtk_ovl_layer_config(struct mtk_ddp_comp *comp, unsigned int idx,
> mtk_ovl_layer_on(comp, idx);
> }
>
> +static void mtk_ovl_bgclr_in_on(struct mtk_ddp_comp *comp)
> +{
> + unsigned int reg;
> +
> + reg = readl(comp->regs + DISP_REG_OVL_DATAPATH_CON);
> + reg = reg | OVL_BGCLR_SEL_IN;
> + writel(reg, comp->regs + DISP_REG_OVL_DATAPATH_CON);
> +}
> +
> +static void mtk_ovl_bgclr_in_off(struct mtk_ddp_comp *comp)
> +{
> + unsigned int reg;
> +
> + reg = readl(comp->regs + DISP_REG_OVL_DATAPATH_CON);
> + reg = reg & ~OVL_BGCLR_SEL_IN;
> + writel(reg, comp->regs + DISP_REG_OVL_DATAPATH_CON);
> +}
> +
> static const struct mtk_ddp_comp_funcs mtk_disp_ovl_funcs = {
> .config = mtk_ovl_config,
> .start = mtk_ovl_start,
> @@ -247,6 +267,8 @@ static void mtk_ovl_layer_config(struct mtk_ddp_comp *comp, unsigned int idx,
> .layer_on = mtk_ovl_layer_on,
> .layer_off = mtk_ovl_layer_off,
> .layer_config = mtk_ovl_layer_config,
> + .bgclr_in_on = mtk_ovl_bgclr_in_on,
> + .bgclr_in_off = mtk_ovl_bgclr_in_off,
> };
>
> static int mtk_disp_ovl_bind(struct device *dev, struct device *master,
WARNING: multiple messages have this Message-ID (diff)
From: CK Hu <ck.hu@mediatek.com>
To: <yongqiang.niu@mediatek.com>
Cc: Mark Rutland <mark.rutland@arm.com>,
devicetree@vger.kernel.org,
Philipp Zabel <p.zabel@pengutronix.de>,
David Airlie <airlied@linux.ie>,
linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
Rob Herring <robh+dt@kernel.org>,
linux-mediatek@lists.infradead.org,
Daniel Vetter <daniel@ffwll.ch>,
Matthias Brugger <matthias.bgg@gmail.com>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v5, 21/32] drm/mediatek: add background color input select function for ovl/ovl_2l
Date: Wed, 9 Oct 2019 17:24:40 +0800 [thread overview]
Message-ID: <1570613080.7713.6.camel@mtksdaap41> (raw)
In-Reply-To: <1567090254-15566-22-git-send-email-yongqiang.niu@mediatek.com>
Hi, Yongqiang:
On Thu, 2019-08-29 at 22:50 +0800, yongqiang.niu@mediatek.com wrote:
> From: Yongqiang Niu <yongqiang.niu@mediatek.com>
>
> This patch add background color input select function for ovl/ovl_2l
>
> ovl include 4 DRAM layer and 1 background color layer
> ovl_2l include 4 DRAM layer and 1 background color layer
> DRAM layer frame buffer data from render hardware, GPU for example.
> backgournd color layer is embed in ovl/ovl_2l, we can only set
> it color, but not support DRAM frame buffer.
>
> for ovl0->ovl0_2l direct link usecase,
> we need set ovl0_2l background color intput select from ovl0
> if render send DRAM buffer layer number <=4, all these layer read
> by ovl.
> layer0 is at the bottom of all layers.
> layer3 is at the top of all layers.
> if render send DRAM buffer layer numbfer >=4 && <=6
> ovl0 read layer0~3
> ovl0_2l read layer4~5
> layer5 is at the top ot all these layers.
>
> the decision of how to setting ovl0/ovl0_2l read these layer data
> is controlled in mtk crtc, which will be another patch
>
Applied to mediatek-drm-next-5.5 [1], thanks.
[1]
https://github.com/ckhu-mediatek/linux.git-tags/commits/mediatek-drm-next-5.5
Regards,
CK
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> Reviewed-by: CK Hu <ck.hu@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 22 ++++++++++++++++++++++
> 1 file changed, 22 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> index baef066..eb3bf85 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> @@ -19,6 +19,8 @@
> #define DISP_REG_OVL_EN 0x000c
> #define DISP_REG_OVL_RST 0x0014
> #define DISP_REG_OVL_ROI_SIZE 0x0020
> +#define DISP_REG_OVL_DATAPATH_CON 0x0024
> +#define OVL_BGCLR_SEL_IN BIT(2)
> #define DISP_REG_OVL_ROI_BGCLR 0x0028
> #define DISP_REG_OVL_SRC_CON 0x002c
> #define DISP_REG_OVL_CON(n) (0x0030 + 0x20 * (n))
> @@ -237,6 +239,24 @@ static void mtk_ovl_layer_config(struct mtk_ddp_comp *comp, unsigned int idx,
> mtk_ovl_layer_on(comp, idx);
> }
>
> +static void mtk_ovl_bgclr_in_on(struct mtk_ddp_comp *comp)
> +{
> + unsigned int reg;
> +
> + reg = readl(comp->regs + DISP_REG_OVL_DATAPATH_CON);
> + reg = reg | OVL_BGCLR_SEL_IN;
> + writel(reg, comp->regs + DISP_REG_OVL_DATAPATH_CON);
> +}
> +
> +static void mtk_ovl_bgclr_in_off(struct mtk_ddp_comp *comp)
> +{
> + unsigned int reg;
> +
> + reg = readl(comp->regs + DISP_REG_OVL_DATAPATH_CON);
> + reg = reg & ~OVL_BGCLR_SEL_IN;
> + writel(reg, comp->regs + DISP_REG_OVL_DATAPATH_CON);
> +}
> +
> static const struct mtk_ddp_comp_funcs mtk_disp_ovl_funcs = {
> .config = mtk_ovl_config,
> .start = mtk_ovl_start,
> @@ -247,6 +267,8 @@ static void mtk_ovl_layer_config(struct mtk_ddp_comp *comp, unsigned int idx,
> .layer_on = mtk_ovl_layer_on,
> .layer_off = mtk_ovl_layer_off,
> .layer_config = mtk_ovl_layer_config,
> + .bgclr_in_on = mtk_ovl_bgclr_in_on,
> + .bgclr_in_off = mtk_ovl_bgclr_in_off,
> };
>
> static int mtk_disp_ovl_bind(struct device *dev, struct device *master,
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next prev parent reply other threads:[~2019-10-09 9:24 UTC|newest]
Thread overview: 217+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-29 14:50 [PATCH v5, 00/32] add drm support for MT8183 yongqiang.niu
2019-08-29 14:50 ` yongqiang.niu
2019-08-29 14:50 ` yongqiang.niu
2019-08-29 14:50 ` [PATCH v5, 01/32] dt-bindings: mediatek: add binding for mt8183 display yongqiang.niu
2019-08-29 14:50 ` yongqiang.niu
2019-08-29 14:50 ` yongqiang.niu-NuS5LvNUpcJWk0Htik3J/w
2019-08-30 5:15 ` CK Hu
2019-08-30 5:15 ` CK Hu
2019-08-30 5:15 ` CK Hu
2019-08-29 14:50 ` [PATCH v5, 02/32] dt-bindings: mediatek: add ovl_2l description " yongqiang.niu
2019-08-29 14:50 ` yongqiang.niu
2019-08-29 14:50 ` yongqiang.niu
2019-09-04 1:44 ` CK Hu
2019-09-04 1:44 ` CK Hu
2019-09-04 1:44 ` CK Hu
2019-08-29 14:50 ` [PATCH v5, 03/32] dt-bindings: mediatek: add ccorr " yongqiang.niu
2019-08-29 14:50 ` yongqiang.niu
2019-08-29 14:50 ` yongqiang.niu
2019-09-04 1:44 ` CK Hu
2019-09-04 1:44 ` CK Hu
2019-09-04 1:44 ` CK Hu
2019-08-29 14:50 ` [PATCH v5, 04/32] dt-bindings: mediatek: add dither " yongqiang.niu
2019-08-29 14:50 ` yongqiang.niu
2019-08-29 14:50 ` yongqiang.niu
2019-09-04 1:45 ` CK Hu
2019-09-04 1:45 ` CK Hu
2019-09-04 1:45 ` CK Hu
2019-08-29 14:50 ` [PATCH v5, 05/32] dt-bindings: mediatek: add mutex " yongqiang.niu
2019-08-29 14:50 ` yongqiang.niu
2019-08-29 14:50 ` yongqiang.niu
2019-09-02 13:38 ` Rob Herring
2019-09-02 13:38 ` Rob Herring
2019-09-02 13:38 ` Rob Herring
2019-09-04 1:45 ` CK Hu
2019-09-04 1:45 ` CK Hu
2019-09-04 1:45 ` CK Hu
2019-08-29 14:50 ` [PATCH v5, 06/32] arm64: dts: add display nodes for mt8183 yongqiang.niu
2019-08-29 14:50 ` yongqiang.niu
2019-08-29 14:50 ` yongqiang.niu
2019-08-29 14:50 ` [PATCH v5, 07/32] drm/mediatek: add mutex mod into ddp private data yongqiang.niu
2019-08-29 14:50 ` yongqiang.niu
2019-08-29 14:50 ` yongqiang.niu
2019-10-09 9:31 ` CK Hu
2019-10-09 9:31 ` CK Hu
2019-10-09 9:31 ` CK Hu
2019-08-29 14:50 ` [PATCH v5, 08/32] drm/mediatek: add mutex mod register offset " yongqiang.niu
2019-08-29 14:50 ` yongqiang.niu
2019-08-29 14:50 ` yongqiang.niu-NuS5LvNUpcJWk0Htik3J/w
2019-10-09 9:32 ` CK Hu
2019-10-09 9:32 ` CK Hu
2019-10-09 9:32 ` CK Hu
2019-08-29 14:50 ` [PATCH v5, 09/32] drm/mediatek: add mutex sof " yongqiang.niu
2019-08-29 14:50 ` yongqiang.niu
2019-08-29 14:50 ` yongqiang.niu
2019-10-09 9:33 ` CK Hu
2019-10-09 9:33 ` CK Hu
2019-10-09 9:33 ` CK Hu
2019-08-29 14:50 ` [PATCH v5, 10/32] drm/mediatek: add mutex sof register offset " yongqiang.niu
2019-08-29 14:50 ` yongqiang.niu
2019-08-29 14:50 ` yongqiang.niu
2019-10-09 9:33 ` CK Hu
2019-10-09 9:33 ` CK Hu
2019-10-09 9:33 ` CK Hu
2019-08-29 14:50 ` [PATCH v5, 11/32] drm/mediatek: split DISP_REG_CONFIG_DSI_SEL setting into another use case yongqiang.niu
2019-08-29 14:50 ` yongqiang.niu
2019-08-29 14:50 ` yongqiang.niu
2019-08-30 5:21 ` CK Hu
2019-08-30 5:21 ` CK Hu
2019-08-30 5:21 ` CK Hu
2019-08-29 14:50 ` [PATCH v5, 12/32] drm/mediatek: add mmsys private data for ddp path config yongqiang.niu
2019-08-29 14:50 ` yongqiang.niu
2019-08-29 14:50 ` yongqiang.niu
2019-08-30 5:27 ` CK Hu
2019-08-30 5:27 ` CK Hu
2019-08-30 5:27 ` CK Hu
2019-08-30 5:40 ` CK Hu
2019-08-30 5:40 ` CK Hu
2019-08-30 5:40 ` CK Hu
2019-08-29 14:50 ` [PATCH v5, 13/32] drm/mediatek: move rdma sout from mtk_ddp_mout_en into mtk_ddp_sout_sel yongqiang.niu
2019-08-29 14:50 ` yongqiang.niu
2019-08-29 14:50 ` yongqiang.niu
2019-08-30 5:41 ` CK Hu
2019-08-30 5:41 ` CK Hu
2019-08-30 5:41 ` CK Hu
2019-08-29 14:50 ` [PATCH v5, 14/32] drm/mediatek: add ddp component CCORR yongqiang.niu
2019-08-29 14:50 ` yongqiang.niu
2019-08-29 14:50 ` yongqiang.niu
2019-10-09 9:10 ` CK Hu
2019-10-09 9:10 ` CK Hu
2019-10-09 9:10 ` CK Hu
2019-08-29 14:50 ` [PATCH v5, 15/32] drm/mediatek: add commponent OVL_2L0 yongqiang.niu
2019-08-29 14:50 ` yongqiang.niu
2019-08-29 14:50 ` yongqiang.niu
2019-10-09 9:17 ` CK Hu
2019-10-09 9:17 ` CK Hu
2019-10-09 9:17 ` CK Hu
2019-08-29 14:50 ` [PATCH v5, 16/32] drm/mediatek: add component OVL_2L1 yongqiang.niu
2019-08-29 14:50 ` yongqiang.niu
2019-08-29 14:50 ` yongqiang.niu
2019-10-09 9:18 ` CK Hu
2019-10-09 9:18 ` CK Hu
2019-10-09 9:18 ` CK Hu
2019-08-29 14:50 ` [PATCH v5, 17/32] drm/mediatek: add component DITHER yongqiang.niu
2019-08-29 14:50 ` yongqiang.niu
2019-08-29 14:50 ` yongqiang.niu
2019-10-09 9:11 ` CK Hu
2019-10-09 9:11 ` CK Hu
2019-10-09 9:11 ` CK Hu
2019-08-29 14:50 ` [PATCH v5, 18/32] drm/mediatek: add gmc_bits for ovl private data yongqiang.niu
2019-08-29 14:50 ` yongqiang.niu
2019-08-29 14:50 ` yongqiang.niu
2019-10-09 9:19 ` CK Hu
2019-10-09 9:19 ` CK Hu
2019-10-09 9:19 ` CK Hu
2019-08-29 14:50 ` [PATCH v5, 19/32] drm/medaitek: add layer_nr " yongqiang.niu
2019-08-29 14:50 ` yongqiang.niu
2019-08-29 14:50 ` yongqiang.niu
2019-10-09 9:20 ` CK Hu
2019-10-09 9:20 ` CK Hu
2019-10-09 9:20 ` CK Hu
2019-08-29 14:50 ` [PATCH v5, 20/32] drm/mediatek: add function to background color input select for ovl/ovl_2l direct link yongqiang.niu
2019-08-29 14:50 ` yongqiang.niu
2019-08-29 14:50 ` yongqiang.niu
2019-10-09 9:24 ` CK Hu
2019-10-09 9:24 ` CK Hu
2019-10-09 9:24 ` CK Hu
2019-08-29 14:50 ` [PATCH v5, 21/32] drm/mediatek: add background color input select function for ovl/ovl_2l yongqiang.niu
2019-08-29 14:50 ` yongqiang.niu
2019-08-29 14:50 ` yongqiang.niu
2019-10-09 9:24 ` CK Hu [this message]
2019-10-09 9:24 ` CK Hu
2019-10-09 9:24 ` CK Hu
2019-08-29 14:50 ` [PATCH v5, 22/32] drm/mediatek: add ovl0/ovl_2l0 usecase yongqiang.niu
2019-08-29 14:50 ` yongqiang.niu
2019-08-29 14:50 ` yongqiang.niu
2019-08-30 5:58 ` CK Hu
2019-08-30 5:58 ` CK Hu
2019-08-30 5:58 ` CK Hu
2019-09-02 8:11 ` CK Hu
2019-09-02 8:11 ` CK Hu
2019-09-02 8:11 ` CK Hu
2019-10-09 9:29 ` CK Hu
2019-10-09 9:29 ` CK Hu
2019-10-09 9:29 ` CK Hu
2019-08-29 14:50 ` [PATCH v5, 23/32] drm/mediatek: distinguish ovl and ovl_2l by layer_nr yongqiang.niu
2019-08-29 14:50 ` yongqiang.niu
2019-08-29 14:50 ` yongqiang.niu
2019-10-09 9:28 ` CK Hu
2019-10-09 9:28 ` CK Hu
2019-10-09 9:28 ` CK Hu
2019-08-29 14:50 ` [PATCH v5, 24/32] drm/mediatek: add clock property check before get it yongqiang.niu
2019-08-29 14:50 ` yongqiang.niu
2019-08-29 14:50 ` yongqiang.niu
2019-08-30 6:11 ` CK Hu
2019-08-30 6:11 ` CK Hu
2019-08-30 6:11 ` CK Hu
2019-10-09 9:36 ` CK Hu
2019-10-09 9:36 ` CK Hu
2019-10-09 9:36 ` CK Hu
2019-08-29 14:50 ` [PATCH v5, 25/32] drm/mediatek: add connection from OVL0 to OVL_2L0 yongqiang.niu
2019-08-29 14:50 ` yongqiang.niu
2019-08-29 14:50 ` yongqiang.niu
2019-08-30 6:20 ` CK Hu
2019-08-30 6:20 ` CK Hu
2019-08-30 6:20 ` CK Hu
2019-08-29 14:50 ` [PATCH v5, 26/32] drm/mediatek: add connection from RDMA0 to COLOR0 yongqiang.niu
2019-08-29 14:50 ` yongqiang.niu
2019-08-29 14:50 ` yongqiang.niu
2019-08-30 6:23 ` CK Hu
2019-08-30 6:23 ` CK Hu
2019-08-30 6:23 ` CK Hu
2019-08-29 14:50 ` [PATCH v5, 27/32] drm/mediatek: add connection from RDMA1 to DSI0 yongqiang.niu
2019-08-29 14:50 ` yongqiang.niu
2019-08-29 14:50 ` yongqiang.niu
2019-08-30 6:25 ` CK Hu
2019-08-30 6:25 ` CK Hu
2019-08-30 6:25 ` CK Hu
2019-08-29 14:50 ` [PATCH v5, 28/32] drm/mediatek: add connection from OVL_2L0 to RDMA0 yongqiang.niu
2019-08-29 14:50 ` yongqiang.niu
2019-08-29 14:50 ` yongqiang.niu
2019-08-30 6:30 ` CK Hu
2019-08-30 6:30 ` CK Hu
2019-08-30 6:30 ` CK Hu
2019-08-29 14:50 ` [PATCH v5, 29/32] drm/mediatek: add connection from OVL_2L1 to RDMA1 yongqiang.niu
2019-08-29 14:50 ` yongqiang.niu
2019-08-29 14:50 ` yongqiang.niu
2019-08-30 6:33 ` CK Hu
2019-08-30 6:33 ` CK Hu
2019-08-30 6:33 ` CK Hu
2019-08-29 14:50 ` [PATCH v5, 30/32] drm/mediatek: add connection from DITHER0 to DSI0 yongqiang.niu
2019-08-29 14:50 ` yongqiang.niu
2019-08-29 14:50 ` yongqiang.niu
2019-08-30 6:34 ` CK Hu
2019-08-30 6:34 ` CK Hu
2019-08-30 6:34 ` CK Hu
2019-08-29 14:50 ` [PATCH v5, 31/32] drm/mediatek: add connection from RDMA0 " yongqiang.niu
2019-08-29 14:50 ` yongqiang.niu
2019-08-29 14:50 ` yongqiang.niu
2019-08-30 6:36 ` CK Hu
2019-08-30 6:36 ` CK Hu
2019-08-30 6:36 ` CK Hu
2019-08-29 14:50 ` [PATCH v5, 32/32] drm/mediatek: add support for mediatek SOC MT8183 yongqiang.niu
2019-08-29 14:50 ` yongqiang.niu
2019-08-29 14:50 ` yongqiang.niu
2019-08-30 6:38 ` CK Hu
2019-08-30 6:38 ` CK Hu
2019-08-30 6:38 ` CK Hu
2019-09-05 7:17 ` CK Hu
2019-09-05 7:17 ` CK Hu
2019-09-05 7:17 ` CK Hu
2020-05-21 10:52 ` Matthias Brugger
2020-05-21 10:52 ` Matthias Brugger
2020-05-21 10:52 ` Matthias Brugger
2020-05-21 10:52 ` Matthias Brugger
2019-10-09 9:47 ` [PATCH v5, 00/32] add drm support for MT8183 CK Hu
2019-10-09 9:47 ` CK Hu
2019-10-09 9:47 ` CK Hu
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