From: Rajan Vaja <rajan.vaja@xilinx.com> To: mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, michal.simek@xilinx.com, m.tretter@pengutronix.de, jolly.shah@xilinx.com, dan.carpenter@oracle.com, gustavo@embeddedor.com, tejas.patel@xilinx.com, nava.manne@xilinx.com, ravi.patel@xilinx.com Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Rajan Vaja <rajan.vaja@xilinx.com> Subject: [PATCH 7/7] clk: zynqmp: Fix fractional clock check Date: Tue, 12 Nov 2019 05:16:20 -0800 [thread overview] Message-ID: <1573564580-9006-8-git-send-email-rajan.vaja@xilinx.com> (raw) In-Reply-To: <1573564580-9006-1-git-send-email-rajan.vaja@xilinx.com> Firmware driver sets BIT(4) to BIT(7) as custom type flags. To make divider as fractional divider firmware sets BIT(4). So add support for custom type flag and use BIT(4) of custom type flag as CLOCK_FRAC bit. Add a new field to the clock_topology to store custom type flags. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> --- drivers/clk/zynqmp/clk-zynqmp.h | 1 + drivers/clk/zynqmp/clkc.c | 4 ++++ drivers/clk/zynqmp/divider.c | 7 +++---- 3 files changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/clk/zynqmp/clk-zynqmp.h b/drivers/clk/zynqmp/clk-zynqmp.h index fec9a15..5beeb41 100644 --- a/drivers/clk/zynqmp/clk-zynqmp.h +++ b/drivers/clk/zynqmp/clk-zynqmp.h @@ -30,6 +30,7 @@ struct clock_topology { u32 type; u32 flag; u32 type_flag; + u8 custom_type_flag; }; struct clk_hw *zynqmp_clk_register_pll(const char *name, u32 clk_id, diff --git a/drivers/clk/zynqmp/clkc.c b/drivers/clk/zynqmp/clkc.c index 10e89f2..4dd8413 100644 --- a/drivers/clk/zynqmp/clkc.c +++ b/drivers/clk/zynqmp/clkc.c @@ -84,6 +84,7 @@ struct name_resp { struct topology_resp { #define CLK_TOPOLOGY_TYPE GENMASK(3, 0) +#define CLK_TOPOLOGY_CUSTOM_TYPE_FLAGS GENMASK(7, 4) #define CLK_TOPOLOGY_FLAGS GENMASK(23, 8) #define CLK_TOPOLOGY_TYPE_FLAGS GENMASK(31, 24) u32 topology[CLK_GET_TOPOLOGY_RESP_WORDS]; @@ -396,6 +397,9 @@ static int __zynqmp_clock_get_topology(struct clock_topology *topology, topology[*nnodes].type_flag = FIELD_GET(CLK_TOPOLOGY_TYPE_FLAGS, response->topology[i]); + topology[*nnodes].custom_type_flag = + FIELD_GET(CLK_TOPOLOGY_CUSTOM_TYPE_FLAGS, + response->topology[i]); (*nnodes)++; } diff --git a/drivers/clk/zynqmp/divider.c b/drivers/clk/zynqmp/divider.c index 67aa88c..e700504 100644 --- a/drivers/clk/zynqmp/divider.c +++ b/drivers/clk/zynqmp/divider.c @@ -25,7 +25,7 @@ #define to_zynqmp_clk_divider(_hw) \ container_of(_hw, struct zynqmp_clk_divider, hw) -#define CLK_FRAC BIT(13) /* has a fractional parent */ +#define CLK_FRAC BIT(4) /* has a fractional parent */ /** * struct zynqmp_clk_divider - adjustable divider clock @@ -279,13 +279,12 @@ struct clk_hw *zynqmp_clk_register_divider(const char *name, init.name = name; init.ops = &zynqmp_clk_divider_ops; - /* CLK_FRAC is not defined in the common clk framework */ - init.flags = nodes->flag & ~CLK_FRAC; + init.flags = nodes->flag; init.parent_names = parents; init.num_parents = 1; /* struct clk_divider assignments */ - div->is_frac = !!(nodes->flag & CLK_FRAC); + div->is_frac = !!(nodes->custom_type_flag & CLK_FRAC); div->flags = nodes->type_flag; div->hw.init = &init; div->clk_id = clk_id; -- 2.7.4
WARNING: multiple messages have this Message-ID (diff)
From: Rajan Vaja <rajan.vaja@xilinx.com> To: mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, michal.simek@xilinx.com, m.tretter@pengutronix.de, jolly.shah@xilinx.com, dan.carpenter@oracle.com, gustavo@embeddedor.com, tejas.patel@xilinx.com, nava.manne@xilinx.com, ravi.patel@xilinx.com Cc: devicetree@vger.kernel.org, Rajan Vaja <rajan.vaja@xilinx.com>, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 7/7] clk: zynqmp: Fix fractional clock check Date: Tue, 12 Nov 2019 05:16:20 -0800 [thread overview] Message-ID: <1573564580-9006-8-git-send-email-rajan.vaja@xilinx.com> (raw) In-Reply-To: <1573564580-9006-1-git-send-email-rajan.vaja@xilinx.com> Firmware driver sets BIT(4) to BIT(7) as custom type flags. To make divider as fractional divider firmware sets BIT(4). So add support for custom type flag and use BIT(4) of custom type flag as CLOCK_FRAC bit. Add a new field to the clock_topology to store custom type flags. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> --- drivers/clk/zynqmp/clk-zynqmp.h | 1 + drivers/clk/zynqmp/clkc.c | 4 ++++ drivers/clk/zynqmp/divider.c | 7 +++---- 3 files changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/clk/zynqmp/clk-zynqmp.h b/drivers/clk/zynqmp/clk-zynqmp.h index fec9a15..5beeb41 100644 --- a/drivers/clk/zynqmp/clk-zynqmp.h +++ b/drivers/clk/zynqmp/clk-zynqmp.h @@ -30,6 +30,7 @@ struct clock_topology { u32 type; u32 flag; u32 type_flag; + u8 custom_type_flag; }; struct clk_hw *zynqmp_clk_register_pll(const char *name, u32 clk_id, diff --git a/drivers/clk/zynqmp/clkc.c b/drivers/clk/zynqmp/clkc.c index 10e89f2..4dd8413 100644 --- a/drivers/clk/zynqmp/clkc.c +++ b/drivers/clk/zynqmp/clkc.c @@ -84,6 +84,7 @@ struct name_resp { struct topology_resp { #define CLK_TOPOLOGY_TYPE GENMASK(3, 0) +#define CLK_TOPOLOGY_CUSTOM_TYPE_FLAGS GENMASK(7, 4) #define CLK_TOPOLOGY_FLAGS GENMASK(23, 8) #define CLK_TOPOLOGY_TYPE_FLAGS GENMASK(31, 24) u32 topology[CLK_GET_TOPOLOGY_RESP_WORDS]; @@ -396,6 +397,9 @@ static int __zynqmp_clock_get_topology(struct clock_topology *topology, topology[*nnodes].type_flag = FIELD_GET(CLK_TOPOLOGY_TYPE_FLAGS, response->topology[i]); + topology[*nnodes].custom_type_flag = + FIELD_GET(CLK_TOPOLOGY_CUSTOM_TYPE_FLAGS, + response->topology[i]); (*nnodes)++; } diff --git a/drivers/clk/zynqmp/divider.c b/drivers/clk/zynqmp/divider.c index 67aa88c..e700504 100644 --- a/drivers/clk/zynqmp/divider.c +++ b/drivers/clk/zynqmp/divider.c @@ -25,7 +25,7 @@ #define to_zynqmp_clk_divider(_hw) \ container_of(_hw, struct zynqmp_clk_divider, hw) -#define CLK_FRAC BIT(13) /* has a fractional parent */ +#define CLK_FRAC BIT(4) /* has a fractional parent */ /** * struct zynqmp_clk_divider - adjustable divider clock @@ -279,13 +279,12 @@ struct clk_hw *zynqmp_clk_register_divider(const char *name, init.name = name; init.ops = &zynqmp_clk_divider_ops; - /* CLK_FRAC is not defined in the common clk framework */ - init.flags = nodes->flag & ~CLK_FRAC; + init.flags = nodes->flag; init.parent_names = parents; init.num_parents = 1; /* struct clk_divider assignments */ - div->is_frac = !!(nodes->flag & CLK_FRAC); + div->is_frac = !!(nodes->custom_type_flag & CLK_FRAC); div->flags = nodes->type_flag; div->hw.init = &init; div->clk_id = clk_id; -- 2.7.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2019-11-12 13:17 UTC|newest] Thread overview: 72+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-11-12 13:16 [PATCH 0/7] clk: zynqmp: Extend and fix zynqmp clock driver Rajan Vaja 2019-11-12 13:16 ` Rajan Vaja 2019-11-12 13:16 ` [PATCH 1/7] dt-bindings: clock: Add bindings for versal " Rajan Vaja 2019-11-12 13:16 ` Rajan Vaja 2019-11-12 22:51 ` Stephen Boyd 2019-11-12 22:51 ` Stephen Boyd 2019-11-18 17:30 ` Rob Herring 2019-11-18 17:30 ` Rob Herring 2019-11-12 13:16 ` [PATCH 2/7] clk: zynqmp: Extend driver for versal Rajan Vaja 2019-11-12 13:16 ` Rajan Vaja 2019-11-12 13:16 ` [PATCH 3/7] clk: zynqmp: Warn user if clock user are more than allowed Rajan Vaja 2019-11-12 13:16 ` Rajan Vaja 2019-11-21 14:31 ` Michael Tretter 2019-11-21 14:31 ` Michael Tretter 2019-11-12 13:16 ` [PATCH 4/7] clk: zynqmp: Add support for get max divider Rajan Vaja 2019-11-12 13:16 ` Rajan Vaja 2019-11-21 14:33 ` Michael Tretter 2019-11-21 14:33 ` Michael Tretter 2019-11-12 13:16 ` [PATCH 5/7] clk: zynqmp: Fix divider calculation Rajan Vaja 2019-11-12 13:16 ` Rajan Vaja 2019-11-12 13:16 ` [PATCH 6/7] clk: zynqmp: Add support for clock with CLK_DIVIDER_POWER_OF_TWO flag Rajan Vaja 2019-11-12 13:16 ` Rajan Vaja 2019-11-12 13:16 ` Rajan Vaja [this message] 2019-11-12 13:16 ` [PATCH 7/7] clk: zynqmp: Fix fractional clock check Rajan Vaja 2019-11-21 14:41 ` Michael Tretter 2019-11-21 14:41 ` Michael Tretter 2019-11-22 9:43 ` [PATCH v2 0/6] clk: zynqmp: Extend and fix zynqmp clock driver Rajan Vaja 2019-11-22 9:43 ` Rajan Vaja 2019-11-22 9:43 ` [PATCH v2 1/6] dt-bindings: clock: Add bindings for versal " Rajan Vaja 2019-11-22 9:43 ` Rajan Vaja 2019-12-04 19:53 ` Rob Herring 2019-12-04 19:53 ` Rob Herring 2019-11-22 9:43 ` [PATCH v2 2/6] clk: zynqmp: Extend driver for versal Rajan Vaja 2019-11-22 9:43 ` Rajan Vaja 2019-11-22 9:43 ` [PATCH v2 3/6] clk: zynqmp: Warn user if clock user are more than allowed Rajan Vaja 2019-11-22 9:43 ` Rajan Vaja 2019-11-22 9:43 ` [PATCH v2 4/6] clk: zynqmp: Add support for get max divider Rajan Vaja 2019-11-22 9:43 ` Rajan Vaja 2019-11-22 9:43 ` [PATCH v2 5/6] clk: zynqmp: Fix divider calculation Rajan Vaja 2019-11-22 9:43 ` Rajan Vaja 2019-11-22 9:43 ` [PATCH v2 6/6] clk: zynqmp: Add support for clock with CLK_DIVIDER_POWER_OF_TWO flag Rajan Vaja 2019-11-22 9:43 ` Rajan Vaja 2019-12-05 6:35 ` [PATCH v3 0/6] clk: zynqmp: Extend and fix zynqmp clock driver Rajan Vaja 2019-12-05 6:35 ` Rajan Vaja 2019-12-05 6:35 ` [PATCH v3 1/6] dt-bindings: clock: Add bindings for versal " Rajan Vaja 2019-12-05 6:35 ` Rajan Vaja 2020-01-23 22:58 ` Stephen Boyd 2020-01-23 22:58 ` Stephen Boyd 2019-12-05 6:35 ` [PATCH v3 2/6] clk: zynqmp: Extend driver for versal Rajan Vaja 2019-12-05 6:35 ` Rajan Vaja 2020-01-23 22:58 ` Stephen Boyd 2020-01-23 22:58 ` Stephen Boyd 2019-12-05 6:35 ` [PATCH v3 3/6] clk: zynqmp: Warn user if clock user are more than allowed Rajan Vaja 2019-12-05 6:35 ` Rajan Vaja 2020-01-23 22:58 ` Stephen Boyd 2020-01-23 22:58 ` Stephen Boyd 2019-12-05 6:35 ` [PATCH v3 4/6] clk: zynqmp: Add support for get max divider Rajan Vaja 2019-12-05 6:35 ` Rajan Vaja 2020-01-23 22:58 ` Stephen Boyd 2020-01-23 22:58 ` Stephen Boyd 2019-12-05 6:35 ` [PATCH v3 5/6] clk: zynqmp: Fix divider calculation Rajan Vaja 2019-12-05 6:35 ` Rajan Vaja 2020-01-23 22:58 ` Stephen Boyd 2020-01-23 22:58 ` Stephen Boyd 2019-12-05 6:35 ` [PATCH v3 6/6] clk: zynqmp: Add support for clock with CLK_DIVIDER_POWER_OF_TWO flag Rajan Vaja 2019-12-05 6:35 ` Rajan Vaja 2020-01-23 22:59 ` Stephen Boyd 2020-01-23 22:59 ` Stephen Boyd 2019-12-12 15:20 ` [PATCH v3 0/6] clk: zynqmp: Extend and fix zynqmp clock driver Michal Simek 2019-12-12 15:20 ` Michal Simek 2020-01-16 11:41 ` Rajan Vaja 2020-01-16 11:41 ` Rajan Vaja
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