From: Stephen Boyd <sboyd@kernel.org> To: Rajan Vaja <rajan.vaja@xilinx.com>, dan.carpenter@oracle.com, gustavo@embeddedor.com, jolly.shah@xilinx.com, m.tretter@pengutronix.de, mark.rutland@arm.com, michal.simek@xilinx.com, mturquette@baylibre.com, nava.manne@xilinx.com, ravi.patel@xilinx.com, robh+dt@kernel.org, tejas.patel@xilinx.com Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Rajan Vaja <rajan.vaja@xilinx.com> Subject: Re: [PATCH 1/7] dt-bindings: clock: Add bindings for versal clock driver Date: Tue, 12 Nov 2019 14:51:46 -0800 [thread overview] Message-ID: <20191112225147.7E59D21783@mail.kernel.org> (raw) In-Reply-To: <1573564580-9006-2-git-send-email-rajan.vaja@xilinx.com> Quoting Rajan Vaja (2019-11-12 05:16:14) > diff --git a/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml > new file mode 100644 > index 0000000..da82f6a > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml > @@ -0,0 +1,67 @@ > +# SPDX-License-Identifier: GPL-2.0 > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/bindings/clock/xlnx,versal-clk.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Xilinx Versal clock controller > + > +maintainers: > + - Michal Simek <michal.simek@xilinx.com> > + - Jolly Shah <jolly.shah@xilinx.com> > + - Rajan Vaja <rajan.vaja@xilinx.com> > + > +description: | > + The clock controller is a h/w block of Xilinx versal clock tree. It reads hardware instead of h/w > + required input clock frequencies from the devicetree and acts as clock > + provider for all clock consumers of PS clocks. See clock_bindings.txt > + for more information on the generic clock bindings. Please drop this last sentence about clock_bindings.txt > + > +properties: > + compatible: > + const: xlnx,versal-clk > + > + "#clock-cells": > + const: 1 > + > + clocks: > + description: List of clock specifiers which are external input > + clocks to the given clock controller. > + minItems: 3 > + maxItems: 3 > + items: > + - description: ref clk > + - description: alternate ref clk > + - description: pl alternate ref clk What is "pl"? Can you clarify? > + > + clock-names: > + minItems: 3 > + maxItems: 3 > + items: > + - const: ref_clk > + - const: alt_ref_clk > + - const: pl_alt_ref_clk > + > +required: > + - compatible > + - "#clock-cells" > + - clocks > + - clock-names > + > +additionalProperties: false > + > +examples: > + - | > + firmware { > + zynqmp_firmware: zynqmp-firmware { > + compatible = "xlnx,zynqmp-firmware"; > + method = "smc"; Is there a way to say in the binding that this must be a child of a xlnx,zynqmp-firmware node? That would be ideal so we can constrain this to that location somehow. > + versal_clk: clock-controller { > + #clock-cells = <1>; > + compatible = "xlnx,versal-clk"; > + clocks = <&ref_clk>, <&alt_ref_clk>, <&pl_alt_ref_clk>; > + clock-names = "ref_clk", "alt_ref_clk", "pl_alt_ref_clk"; > + }; > + }; > + }; > +...
WARNING: multiple messages have this Message-ID (diff)
From: Stephen Boyd <sboyd@kernel.org> To: Rajan Vaja <rajan.vaja@xilinx.com>, dan.carpenter@oracle.com, gustavo@embeddedor.com, jolly.shah@xilinx.com, m.tretter@pengutronix.de, mark.rutland@arm.com, michal.simek@xilinx.com, mturquette@baylibre.com, nava.manne@xilinx.com, ravi.patel@xilinx.com, robh+dt@kernel.org, tejas.patel@xilinx.com Cc: devicetree@vger.kernel.org, Rajan Vaja <rajan.vaja@xilinx.com>, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 1/7] dt-bindings: clock: Add bindings for versal clock driver Date: Tue, 12 Nov 2019 14:51:46 -0800 [thread overview] Message-ID: <20191112225147.7E59D21783@mail.kernel.org> (raw) In-Reply-To: <1573564580-9006-2-git-send-email-rajan.vaja@xilinx.com> Quoting Rajan Vaja (2019-11-12 05:16:14) > diff --git a/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml > new file mode 100644 > index 0000000..da82f6a > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml > @@ -0,0 +1,67 @@ > +# SPDX-License-Identifier: GPL-2.0 > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/bindings/clock/xlnx,versal-clk.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Xilinx Versal clock controller > + > +maintainers: > + - Michal Simek <michal.simek@xilinx.com> > + - Jolly Shah <jolly.shah@xilinx.com> > + - Rajan Vaja <rajan.vaja@xilinx.com> > + > +description: | > + The clock controller is a h/w block of Xilinx versal clock tree. It reads hardware instead of h/w > + required input clock frequencies from the devicetree and acts as clock > + provider for all clock consumers of PS clocks. See clock_bindings.txt > + for more information on the generic clock bindings. Please drop this last sentence about clock_bindings.txt > + > +properties: > + compatible: > + const: xlnx,versal-clk > + > + "#clock-cells": > + const: 1 > + > + clocks: > + description: List of clock specifiers which are external input > + clocks to the given clock controller. > + minItems: 3 > + maxItems: 3 > + items: > + - description: ref clk > + - description: alternate ref clk > + - description: pl alternate ref clk What is "pl"? Can you clarify? > + > + clock-names: > + minItems: 3 > + maxItems: 3 > + items: > + - const: ref_clk > + - const: alt_ref_clk > + - const: pl_alt_ref_clk > + > +required: > + - compatible > + - "#clock-cells" > + - clocks > + - clock-names > + > +additionalProperties: false > + > +examples: > + - | > + firmware { > + zynqmp_firmware: zynqmp-firmware { > + compatible = "xlnx,zynqmp-firmware"; > + method = "smc"; Is there a way to say in the binding that this must be a child of a xlnx,zynqmp-firmware node? That would be ideal so we can constrain this to that location somehow. > + versal_clk: clock-controller { > + #clock-cells = <1>; > + compatible = "xlnx,versal-clk"; > + clocks = <&ref_clk>, <&alt_ref_clk>, <&pl_alt_ref_clk>; > + clock-names = "ref_clk", "alt_ref_clk", "pl_alt_ref_clk"; > + }; > + }; > + }; > +... _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2019-11-12 22:51 UTC|newest] Thread overview: 72+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-11-12 13:16 [PATCH 0/7] clk: zynqmp: Extend and fix zynqmp clock driver Rajan Vaja 2019-11-12 13:16 ` Rajan Vaja 2019-11-12 13:16 ` [PATCH 1/7] dt-bindings: clock: Add bindings for versal " Rajan Vaja 2019-11-12 13:16 ` Rajan Vaja 2019-11-12 22:51 ` Stephen Boyd [this message] 2019-11-12 22:51 ` Stephen Boyd 2019-11-18 17:30 ` Rob Herring 2019-11-18 17:30 ` Rob Herring 2019-11-12 13:16 ` [PATCH 2/7] clk: zynqmp: Extend driver for versal Rajan Vaja 2019-11-12 13:16 ` Rajan Vaja 2019-11-12 13:16 ` [PATCH 3/7] clk: zynqmp: Warn user if clock user are more than allowed Rajan Vaja 2019-11-12 13:16 ` Rajan Vaja 2019-11-21 14:31 ` Michael Tretter 2019-11-21 14:31 ` Michael Tretter 2019-11-12 13:16 ` [PATCH 4/7] clk: zynqmp: Add support for get max divider Rajan Vaja 2019-11-12 13:16 ` Rajan Vaja 2019-11-21 14:33 ` Michael Tretter 2019-11-21 14:33 ` Michael Tretter 2019-11-12 13:16 ` [PATCH 5/7] clk: zynqmp: Fix divider calculation Rajan Vaja 2019-11-12 13:16 ` Rajan Vaja 2019-11-12 13:16 ` [PATCH 6/7] clk: zynqmp: Add support for clock with CLK_DIVIDER_POWER_OF_TWO flag Rajan Vaja 2019-11-12 13:16 ` Rajan Vaja 2019-11-12 13:16 ` [PATCH 7/7] clk: zynqmp: Fix fractional clock check Rajan Vaja 2019-11-12 13:16 ` Rajan Vaja 2019-11-21 14:41 ` Michael Tretter 2019-11-21 14:41 ` Michael Tretter 2019-11-22 9:43 ` [PATCH v2 0/6] clk: zynqmp: Extend and fix zynqmp clock driver Rajan Vaja 2019-11-22 9:43 ` Rajan Vaja 2019-11-22 9:43 ` [PATCH v2 1/6] dt-bindings: clock: Add bindings for versal " Rajan Vaja 2019-11-22 9:43 ` Rajan Vaja 2019-12-04 19:53 ` Rob Herring 2019-12-04 19:53 ` Rob Herring 2019-11-22 9:43 ` [PATCH v2 2/6] clk: zynqmp: Extend driver for versal Rajan Vaja 2019-11-22 9:43 ` Rajan Vaja 2019-11-22 9:43 ` [PATCH v2 3/6] clk: zynqmp: Warn user if clock user are more than allowed Rajan Vaja 2019-11-22 9:43 ` Rajan Vaja 2019-11-22 9:43 ` [PATCH v2 4/6] clk: zynqmp: Add support for get max divider Rajan Vaja 2019-11-22 9:43 ` Rajan Vaja 2019-11-22 9:43 ` [PATCH v2 5/6] clk: zynqmp: Fix divider calculation Rajan Vaja 2019-11-22 9:43 ` Rajan Vaja 2019-11-22 9:43 ` [PATCH v2 6/6] clk: zynqmp: Add support for clock with CLK_DIVIDER_POWER_OF_TWO flag Rajan Vaja 2019-11-22 9:43 ` Rajan Vaja 2019-12-05 6:35 ` [PATCH v3 0/6] clk: zynqmp: Extend and fix zynqmp clock driver Rajan Vaja 2019-12-05 6:35 ` Rajan Vaja 2019-12-05 6:35 ` [PATCH v3 1/6] dt-bindings: clock: Add bindings for versal " Rajan Vaja 2019-12-05 6:35 ` Rajan Vaja 2020-01-23 22:58 ` Stephen Boyd 2020-01-23 22:58 ` Stephen Boyd 2019-12-05 6:35 ` [PATCH v3 2/6] clk: zynqmp: Extend driver for versal Rajan Vaja 2019-12-05 6:35 ` Rajan Vaja 2020-01-23 22:58 ` Stephen Boyd 2020-01-23 22:58 ` Stephen Boyd 2019-12-05 6:35 ` [PATCH v3 3/6] clk: zynqmp: Warn user if clock user are more than allowed Rajan Vaja 2019-12-05 6:35 ` Rajan Vaja 2020-01-23 22:58 ` Stephen Boyd 2020-01-23 22:58 ` Stephen Boyd 2019-12-05 6:35 ` [PATCH v3 4/6] clk: zynqmp: Add support for get max divider Rajan Vaja 2019-12-05 6:35 ` Rajan Vaja 2020-01-23 22:58 ` Stephen Boyd 2020-01-23 22:58 ` Stephen Boyd 2019-12-05 6:35 ` [PATCH v3 5/6] clk: zynqmp: Fix divider calculation Rajan Vaja 2019-12-05 6:35 ` Rajan Vaja 2020-01-23 22:58 ` Stephen Boyd 2020-01-23 22:58 ` Stephen Boyd 2019-12-05 6:35 ` [PATCH v3 6/6] clk: zynqmp: Add support for clock with CLK_DIVIDER_POWER_OF_TWO flag Rajan Vaja 2019-12-05 6:35 ` Rajan Vaja 2020-01-23 22:59 ` Stephen Boyd 2020-01-23 22:59 ` Stephen Boyd 2019-12-12 15:20 ` [PATCH v3 0/6] clk: zynqmp: Extend and fix zynqmp clock driver Michal Simek 2019-12-12 15:20 ` Michal Simek 2020-01-16 11:41 ` Rajan Vaja 2020-01-16 11:41 ` Rajan Vaja
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