From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> To: Geert Uytterhoeven <geert+renesas@glider.be>, Magnus Damm <magnus.damm@gmail.com>, Rob Herring <robh+dt@kernel.org>, Vinod Koul <vkoul@kernel.org>, Linus Walleij <linus.walleij@linaro.org>, Bartosz Golaszewski <bgolaszewski@baylibre.com>, Thomas Gleixner <tglx@linutronix.de>, Jason Cooper <jason@lakedaemon.net>, Marc Zyngier <maz@kernel.org>, Greg Kroah-Hartman <gregkh@linuxfoundation.org>, Russell King <linux@armlinux.org.uk> Cc: Lad Prabhakar <prabhakar.csengg@gmail.com>, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Subject: [PATCH 16/18] ARM: dts: r8a7742: Add [H]SCIF{A|B} support Date: Wed, 29 Apr 2020 22:56:53 +0100 [thread overview] Message-ID: <1588197415-13747-17-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com> (raw) In-Reply-To: <1588197415-13747-1-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com> Describe [H]SCIF{|A|B} ports in the R8A7742 device tree. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> --- arch/arm/boot/dts/r8a7742.dtsi | 140 ++++++++++++++++++++++++++++++++++++++--- 1 file changed, 130 insertions(+), 10 deletions(-) diff --git a/arch/arm/boot/dts/r8a7742.dtsi b/arch/arm/boot/dts/r8a7742.dtsi index 0febd74..5305214 100644 --- a/arch/arm/boot/dts/r8a7742.dtsi +++ b/arch/arm/boot/dts/r8a7742.dtsi @@ -522,53 +522,173 @@ }; scifa0: serial@e6c40000 { + compatible = "renesas,scifa-r8a7742", + "renesas,rcar-gen2-scifa", "renesas,scifa"; reg = <0 0xe6c40000 0 0x40>; - /* placeholder */ + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 204>; + clock-names = "fck"; + dmas = <&dmac0 0x21>, <&dmac0 0x22>, + <&dmac1 0x21>, <&dmac1 0x22>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 204>; + status = "disabled"; }; scifa1: serial@e6c50000 { + compatible = "renesas,scifa-r8a7742", + "renesas,rcar-gen2-scifa", "renesas,scifa"; reg = <0 0xe6c50000 0 0x40>; - /* placeholder */ + interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 203>; + clock-names = "fck"; + dmas = <&dmac0 0x25>, <&dmac0 0x26>, + <&dmac1 0x25>, <&dmac1 0x26>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 203>; + status = "disabled"; }; scifa2: serial@e6c60000 { + compatible = "renesas,scifa-r8a7742", + "renesas,rcar-gen2-scifa", "renesas,scifa"; reg = <0 0xe6c60000 0 0x40>; - /* placeholder */ + interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 202>; + clock-names = "fck"; + dmas = <&dmac0 0x27>, <&dmac0 0x28>, + <&dmac1 0x27>, <&dmac1 0x28>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 202>; + status = "disabled"; }; scifb0: serial@e6c20000 { + compatible = "renesas,scifb-r8a7742", + "renesas,rcar-gen2-scifb", "renesas,scifb"; reg = <0 0xe6c20000 0 0x100>; - /* placeholder */ + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 206>; + clock-names = "fck"; + dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, + <&dmac1 0x3d>, <&dmac1 0x3e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 206>; + status = "disabled"; }; scifb1: serial@e6c30000 { + compatible = "renesas,scifb-r8a7742", + "renesas,rcar-gen2-scifb", "renesas,scifb"; reg = <0 0xe6c30000 0 0x100>; - /* placeholder */ + interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 207>; + clock-names = "fck"; + dmas = <&dmac0 0x19>, <&dmac0 0x1a>, + <&dmac1 0x19>, <&dmac1 0x1a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 207>; + status = "disabled"; }; scifb2: serial@e6ce0000 { + compatible = "renesas,scifb-r8a7742", + "renesas,rcar-gen2-scifb", "renesas,scifb"; reg = <0 0xe6ce0000 0 0x100>; - /* placeholder */ + interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 216>; + clock-names = "fck"; + dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, + <&dmac1 0x1d>, <&dmac1 0x1e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 216>; + status = "disabled"; }; scif0: serial@e6e60000 { + compatible = "renesas,scif-r8a7742", + "renesas,rcar-gen2-scif", "renesas,scif"; reg = <0 0xe6e60000 0 0x40>; - /* placeholder */ + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 721>, + <&cpg CPG_CORE R8A7742_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x29>, <&dmac0 0x2a>, + <&dmac1 0x29>, <&dmac1 0x2a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 721>; + status = "disabled"; }; scif1: serial@e6e68000 { + compatible = "renesas,scif-r8a7742", + "renesas,rcar-gen2-scif", "renesas,scif"; reg = <0 0xe6e68000 0 0x40>; - /* placeholder */ + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 720>, + <&cpg CPG_CORE R8A7742_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, + <&dmac1 0x2d>, <&dmac1 0x2e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 720>; + status = "disabled"; + }; + + scif2: serial@e6e56000 { + compatible = "renesas,scif-r8a7742", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6e56000 0 0x40>; + interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 310>, + <&cpg CPG_CORE R8A7742_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, + <&dmac1 0x2b>, <&dmac1 0x2c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 310>; + status = "disabled"; }; hscif0: serial@e62c0000 { + compatible = "renesas,hscif-r8a7742", + "renesas,rcar-gen2-hscif", "renesas,hscif"; reg = <0 0xe62c0000 0 0x60>; - /* placeholder */ + interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 717>, + <&cpg CPG_CORE R8A7742_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x39>, <&dmac0 0x3a>, + <&dmac1 0x39>, <&dmac1 0x3a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 717>; + status = "disabled"; }; hscif1: serial@e62c8000 { + compatible = "renesas,hscif-r8a7742", + "renesas,rcar-gen2-hscif", "renesas,hscif"; reg = <0 0xe62c8000 0 0x60>; - /* placeholder */ + interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 716>, + <&cpg CPG_CORE R8A7742_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, + <&dmac1 0x4d>, <&dmac1 0x4e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 716>; + status = "disabled"; }; can0: can@e6e80000 { -- 2.7.4
WARNING: multiple messages have this Message-ID (diff)
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> To: Geert Uytterhoeven <geert+renesas@glider.be>, Magnus Damm <magnus.damm@gmail.com>, Rob Herring <robh+dt@kernel.org>, Vinod Koul <vkoul@kernel.org>, Linus Walleij <linus.walleij@linaro.org>, Bartosz Golaszewski <bgolaszewski@baylibre.com>, Thomas Gleixner <tglx@linutronix.de>, Jason Cooper <jason@lakedaemon.net>, Marc Zyngier <maz@kernel.org>, Greg Kroah-Hartman <gregkh@linuxfoundation.org>, Russell King <linux@armlinux.org.uk> Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>, linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, Lad Prabhakar <prabhakar.csengg@gmail.com>, linux-serial@vger.kernel.org, dmaengine@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 16/18] ARM: dts: r8a7742: Add [H]SCIF{A|B} support Date: Wed, 29 Apr 2020 22:56:53 +0100 [thread overview] Message-ID: <1588197415-13747-17-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com> (raw) In-Reply-To: <1588197415-13747-1-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com> Describe [H]SCIF{|A|B} ports in the R8A7742 device tree. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> --- arch/arm/boot/dts/r8a7742.dtsi | 140 ++++++++++++++++++++++++++++++++++++++--- 1 file changed, 130 insertions(+), 10 deletions(-) diff --git a/arch/arm/boot/dts/r8a7742.dtsi b/arch/arm/boot/dts/r8a7742.dtsi index 0febd74..5305214 100644 --- a/arch/arm/boot/dts/r8a7742.dtsi +++ b/arch/arm/boot/dts/r8a7742.dtsi @@ -522,53 +522,173 @@ }; scifa0: serial@e6c40000 { + compatible = "renesas,scifa-r8a7742", + "renesas,rcar-gen2-scifa", "renesas,scifa"; reg = <0 0xe6c40000 0 0x40>; - /* placeholder */ + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 204>; + clock-names = "fck"; + dmas = <&dmac0 0x21>, <&dmac0 0x22>, + <&dmac1 0x21>, <&dmac1 0x22>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 204>; + status = "disabled"; }; scifa1: serial@e6c50000 { + compatible = "renesas,scifa-r8a7742", + "renesas,rcar-gen2-scifa", "renesas,scifa"; reg = <0 0xe6c50000 0 0x40>; - /* placeholder */ + interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 203>; + clock-names = "fck"; + dmas = <&dmac0 0x25>, <&dmac0 0x26>, + <&dmac1 0x25>, <&dmac1 0x26>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 203>; + status = "disabled"; }; scifa2: serial@e6c60000 { + compatible = "renesas,scifa-r8a7742", + "renesas,rcar-gen2-scifa", "renesas,scifa"; reg = <0 0xe6c60000 0 0x40>; - /* placeholder */ + interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 202>; + clock-names = "fck"; + dmas = <&dmac0 0x27>, <&dmac0 0x28>, + <&dmac1 0x27>, <&dmac1 0x28>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 202>; + status = "disabled"; }; scifb0: serial@e6c20000 { + compatible = "renesas,scifb-r8a7742", + "renesas,rcar-gen2-scifb", "renesas,scifb"; reg = <0 0xe6c20000 0 0x100>; - /* placeholder */ + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 206>; + clock-names = "fck"; + dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, + <&dmac1 0x3d>, <&dmac1 0x3e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 206>; + status = "disabled"; }; scifb1: serial@e6c30000 { + compatible = "renesas,scifb-r8a7742", + "renesas,rcar-gen2-scifb", "renesas,scifb"; reg = <0 0xe6c30000 0 0x100>; - /* placeholder */ + interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 207>; + clock-names = "fck"; + dmas = <&dmac0 0x19>, <&dmac0 0x1a>, + <&dmac1 0x19>, <&dmac1 0x1a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 207>; + status = "disabled"; }; scifb2: serial@e6ce0000 { + compatible = "renesas,scifb-r8a7742", + "renesas,rcar-gen2-scifb", "renesas,scifb"; reg = <0 0xe6ce0000 0 0x100>; - /* placeholder */ + interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 216>; + clock-names = "fck"; + dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, + <&dmac1 0x1d>, <&dmac1 0x1e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 216>; + status = "disabled"; }; scif0: serial@e6e60000 { + compatible = "renesas,scif-r8a7742", + "renesas,rcar-gen2-scif", "renesas,scif"; reg = <0 0xe6e60000 0 0x40>; - /* placeholder */ + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 721>, + <&cpg CPG_CORE R8A7742_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x29>, <&dmac0 0x2a>, + <&dmac1 0x29>, <&dmac1 0x2a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 721>; + status = "disabled"; }; scif1: serial@e6e68000 { + compatible = "renesas,scif-r8a7742", + "renesas,rcar-gen2-scif", "renesas,scif"; reg = <0 0xe6e68000 0 0x40>; - /* placeholder */ + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 720>, + <&cpg CPG_CORE R8A7742_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, + <&dmac1 0x2d>, <&dmac1 0x2e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 720>; + status = "disabled"; + }; + + scif2: serial@e6e56000 { + compatible = "renesas,scif-r8a7742", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6e56000 0 0x40>; + interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 310>, + <&cpg CPG_CORE R8A7742_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, + <&dmac1 0x2b>, <&dmac1 0x2c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 310>; + status = "disabled"; }; hscif0: serial@e62c0000 { + compatible = "renesas,hscif-r8a7742", + "renesas,rcar-gen2-hscif", "renesas,hscif"; reg = <0 0xe62c0000 0 0x60>; - /* placeholder */ + interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 717>, + <&cpg CPG_CORE R8A7742_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x39>, <&dmac0 0x3a>, + <&dmac1 0x39>, <&dmac1 0x3a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 717>; + status = "disabled"; }; hscif1: serial@e62c8000 { + compatible = "renesas,hscif-r8a7742", + "renesas,rcar-gen2-hscif", "renesas,hscif"; reg = <0 0xe62c8000 0 0x60>; - /* placeholder */ + interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 716>, + <&cpg CPG_CORE R8A7742_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, + <&dmac1 0x4d>, <&dmac1 0x4e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 716>; + status = "disabled"; }; can0: can@e6e80000 { -- 2.7.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-04-29 21:59 UTC|newest] Thread overview: 94+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-04-29 21:56 [PATCH 00/18] Add R8A7742/RZG1H board support Lad Prabhakar 2020-04-29 21:56 ` Lad Prabhakar 2020-04-29 21:56 ` [PATCH 01/18] soc: renesas: Add Renesas R8A7742 config option Lad Prabhakar 2020-04-29 21:56 ` Lad Prabhakar 2020-04-30 12:57 ` Geert Uytterhoeven 2020-04-30 12:57 ` Geert Uytterhoeven 2020-04-29 21:56 ` [PATCH 02/18] ARM: shmobile: defconfig: Enable r8a7742 SoC Lad Prabhakar 2020-04-29 21:56 ` Lad Prabhakar 2020-04-30 12:58 ` Geert Uytterhoeven 2020-04-30 12:58 ` Geert Uytterhoeven 2020-04-29 21:56 ` [PATCH 03/18] ARM: multi_v7_defconfig: " Lad Prabhakar 2020-04-29 21:56 ` Lad Prabhakar 2020-04-30 12:59 ` Geert Uytterhoeven 2020-04-30 12:59 ` Geert Uytterhoeven 2020-04-29 21:56 ` [PATCH 04/18] ARM: debug-ll: Add support for r8a7742 Lad Prabhakar 2020-04-29 21:56 ` Lad Prabhakar 2020-04-29 21:59 ` Russell King - ARM Linux admin 2020-04-29 21:59 ` Russell King - ARM Linux admin 2020-04-29 22:03 ` Lad, Prabhakar 2020-04-29 22:03 ` Lad, Prabhakar 2020-04-30 13:03 ` Geert Uytterhoeven 2020-04-30 13:03 ` Geert Uytterhoeven 2020-05-01 8:19 ` Lad, Prabhakar 2020-05-01 8:19 ` Lad, Prabhakar 2020-04-29 21:56 ` [PATCH 05/18] dt-bindings: pinctrl: sh-pfc: Document r8a7742 PFC support Lad Prabhakar 2020-04-29 21:56 ` Lad Prabhakar 2020-04-30 13:04 ` Geert Uytterhoeven 2020-04-30 13:04 ` Geert Uytterhoeven 2020-04-29 21:56 ` [PATCH 06/18] pinctrl: sh-pfc: r8a7790: Add " Lad Prabhakar 2020-04-29 21:56 ` Lad Prabhakar 2020-04-30 13:17 ` Geert Uytterhoeven 2020-04-30 13:17 ` Geert Uytterhoeven 2020-05-01 8:08 ` Lad, Prabhakar 2020-05-01 8:08 ` Lad, Prabhakar 2020-04-29 21:56 ` [PATCH 07/18] ARM: dts: r8a7742: Initial SoC device tree Lad Prabhakar 2020-04-29 21:56 ` Lad Prabhakar 2020-04-30 13:49 ` Geert Uytterhoeven 2020-04-30 13:49 ` Geert Uytterhoeven 2020-05-01 8:15 ` Lad, Prabhakar 2020-05-01 8:15 ` Lad, Prabhakar 2020-04-29 21:56 ` [PATCH 08/18] dt-bindings: irqchip: renesas-irqc: Document r8a7742 bindings Lad Prabhakar 2020-04-29 21:56 ` Lad Prabhakar 2020-04-30 13:52 ` Geert Uytterhoeven 2020-04-30 13:52 ` Geert Uytterhoeven 2020-04-29 21:56 ` [PATCH 09/18] ARM: dts: r8a7742: Add IRQC support Lad Prabhakar 2020-04-29 21:56 ` Lad Prabhakar 2020-04-30 13:54 ` Geert Uytterhoeven 2020-04-30 13:54 ` Geert Uytterhoeven 2020-04-30 14:01 ` Marc Zyngier 2020-04-30 14:01 ` Marc Zyngier 2020-04-30 14:04 ` Geert Uytterhoeven 2020-04-30 14:04 ` Geert Uytterhoeven 2020-04-29 21:56 ` [PATCH 10/18] dt-bindings: rcar-dmac: Document r8a7742 support Lad Prabhakar 2020-04-29 21:56 ` Lad Prabhakar 2020-04-30 13:56 ` Geert Uytterhoeven 2020-04-30 13:56 ` Geert Uytterhoeven 2020-04-29 21:56 ` [PATCH 11/18] ARM: dts: r8a7742: Add SYS-DMAC support Lad Prabhakar 2020-04-29 21:56 ` Lad Prabhakar 2020-04-30 14:00 ` Geert Uytterhoeven 2020-04-30 14:00 ` Geert Uytterhoeven 2020-04-29 21:56 ` [PATCH 12/18] dt-bindings: serial: renesas,scif: Document r8a7742 bindings Lad Prabhakar 2020-04-29 21:56 ` [PATCH 12/18] dt-bindings: serial: renesas, scif: " Lad Prabhakar 2020-04-30 14:01 ` [PATCH 12/18] dt-bindings: serial: renesas,scif: " Geert Uytterhoeven 2020-04-30 14:01 ` [PATCH 12/18] dt-bindings: serial: renesas, scif: " Geert Uytterhoeven 2020-04-29 21:56 ` [PATCH 13/18] dt-bindings: serial: renesas,scifa: " Lad Prabhakar 2020-04-29 21:56 ` [PATCH 13/18] dt-bindings: serial: renesas, scifa: " Lad Prabhakar 2020-04-30 14:02 ` [PATCH 13/18] dt-bindings: serial: renesas,scifa: " Geert Uytterhoeven 2020-04-30 14:02 ` Geert Uytterhoeven 2020-04-29 21:56 ` [PATCH 14/18] dt-bindings: serial: renesas,scifb: " Lad Prabhakar 2020-04-29 21:56 ` [PATCH 14/18] dt-bindings: serial: renesas, scifb: " Lad Prabhakar 2020-04-30 14:03 ` [PATCH 14/18] dt-bindings: serial: renesas,scifb: " Geert Uytterhoeven 2020-04-30 14:03 ` Geert Uytterhoeven 2020-04-29 21:56 ` [PATCH 15/18] dt-bindings: serial: renesas,hscif: " Lad Prabhakar 2020-04-29 21:56 ` [PATCH 15/18] dt-bindings: serial: renesas, hscif: " Lad Prabhakar 2020-04-30 14:03 ` [PATCH 15/18] dt-bindings: serial: renesas,hscif: " Geert Uytterhoeven 2020-04-30 14:03 ` Geert Uytterhoeven 2020-04-29 21:56 ` Lad Prabhakar [this message] 2020-04-29 21:56 ` [PATCH 16/18] ARM: dts: r8a7742: Add [H]SCIF{A|B} support Lad Prabhakar 2020-04-30 14:27 ` Geert Uytterhoeven 2020-04-30 14:27 ` Geert Uytterhoeven 2020-04-29 21:56 ` [PATCH 17/18] dt-bindings: gpio: rcar: Add r8a7742 (RZ/G1H) support Lad Prabhakar 2020-04-29 21:56 ` Lad Prabhakar 2020-04-30 14:28 ` Geert Uytterhoeven 2020-04-30 14:28 ` Geert Uytterhoeven 2020-05-12 14:52 ` Rob Herring 2020-05-12 14:52 ` Rob Herring 2020-05-12 14:56 ` Geert Uytterhoeven 2020-05-12 14:56 ` Geert Uytterhoeven 2020-04-29 21:56 ` [PATCH 18/18] ARM: dts: r8a7742: Add GPIO support Lad Prabhakar 2020-04-29 21:56 ` Lad Prabhakar 2020-04-30 14:37 ` Geert Uytterhoeven 2020-04-30 14:37 ` Geert Uytterhoeven 2020-05-01 8:27 ` [PATCH 00/18] Add R8A7742/RZG1H board support Lad, Prabhakar 2020-05-01 8:27 ` Lad, Prabhakar
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