From: "tip-bot2 for Wei Wang" <tip-bot2@linutronix.de>
To: linux-tip-commits@vger.kernel.org
Cc: "Peter Zijlstra (Intel)" <peterz@infradead.org>,
Wei Wang <wei.w.wang@intel.com>, x86 <x86@kernel.org>,
LKML <linux-kernel@vger.kernel.org>
Subject: [tip: perf/core] perf/x86: Fix variable types for LBR registers
Date: Fri, 03 Jul 2020 08:01:28 -0000 [thread overview]
Message-ID: <159376328837.4006.10960362738687676693.tip-bot2@tip-bot2> (raw)
In-Reply-To: <20200613080958.132489-2-like.xu@linux.intel.com>
The following commit has been merged into the perf/core branch of tip:
Commit-ID: 3cb9d5464c1ceea86f6225089b2f7965989cf316
Gitweb: https://git.kernel.org/tip/3cb9d5464c1ceea86f6225089b2f7965989cf316
Author: Wei Wang <wei.w.wang@intel.com>
AuthorDate: Sat, 13 Jun 2020 16:09:46 +08:00
Committer: Peter Zijlstra <peterz@infradead.org>
CommitterDate: Thu, 02 Jul 2020 15:51:45 +02:00
perf/x86: Fix variable types for LBR registers
The MSR variable type can be 'unsigned int', which uses less memory than
the longer 'unsigned long'. Fix 'struct x86_pmu' for that. The lbr_nr won't
be a negative number, so make it 'unsigned int' as well.
Suggested-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Wei Wang <wei.w.wang@intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/20200613080958.132489-2-like.xu@linux.intel.com
---
arch/x86/events/perf_event.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
index e17a3d8..eb37f6c 100644
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -673,8 +673,8 @@ struct x86_pmu {
/*
* Intel LBR
*/
- unsigned long lbr_tos, lbr_from, lbr_to; /* MSR base regs */
- int lbr_nr; /* hardware stack size */
+ unsigned int lbr_tos, lbr_from, lbr_to,
+ lbr_nr; /* LBR base regs and size */
u64 lbr_sel_mask; /* LBR_SELECT valid bits */
const int *lbr_sel_map; /* lbr_select mappings */
bool lbr_double_abort; /* duplicated lbr aborts */
next prev parent reply other threads:[~2020-07-03 8:01 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-13 8:09 [PATCH v12 00/11] Guest Last Branch Recording Enabling Like Xu
2020-06-13 8:09 ` [PATCH v12 01/11] perf/x86: Fix variable types for LBR registers Like Xu
2020-07-03 8:01 ` tip-bot2 for Wei Wang [this message]
2020-11-09 6:34 ` Andi Kleen
2020-11-11 2:14 ` Xu, Like
2020-06-13 8:09 ` [PATCH v12 02/11] perf/x86/core: Refactor hw->idx checks and cleanup Like Xu
2020-07-03 8:01 ` [tip: perf/core] " tip-bot2 for Like Xu
2020-06-13 8:09 ` [PATCH v12 03/11] perf/x86/lbr: Add interface to get LBR information Like Xu
2020-07-03 8:01 ` [tip: perf/core] " tip-bot2 for Like Xu
2020-06-13 8:09 ` [PATCH v12 04/11] perf/x86: Add constraint to create guest LBR event without hw counter Like Xu
2020-06-13 8:09 ` [PATCH v12 05/11] perf/x86: Keep LBR records unchanged in host context for guest usage Like Xu
2020-06-13 8:09 ` [PATCH v12 06/11] KVM: vmx/pmu: Expose LBR to guest via MSR_IA32_PERF_CAPABILITIES Like Xu
2020-07-08 13:36 ` Andi Kleen
2020-07-08 14:38 ` Xu, Like
2020-06-13 8:09 ` [PATCH v12 07/11] KVM: vmx/pmu: Unmask LBR fields in the MSR_IA32_DEBUGCTLMSR emualtion Like Xu
2020-06-13 9:14 ` Xiaoyao Li
2020-06-13 9:42 ` Xu, Like
2020-07-07 20:21 ` Sean Christopherson
2020-07-08 1:37 ` Xiaoyao Li
2020-07-08 7:06 ` Xu, Like
2020-07-10 16:28 ` Sean Christopherson
2020-06-13 8:09 ` [PATCH v12 08/11] KVM: vmx/pmu: Pass-through LBR msrs when guest LBR event is scheduled Like Xu
2020-06-13 8:09 ` [PATCH v12 09/11] KVM: vmx/pmu: Emulate legacy freezing LBRs on virtual PMI Like Xu
2020-06-13 8:09 ` [PATCH v12 10/11] KVM: vmx/pmu: Reduce the overhead of LBR pass-through or cancellation Like Xu
2020-06-13 8:09 ` [PATCH v12 11/11] KVM: vmx/pmu: Release guest LBR event via lazy release mechanism Like Xu
2020-06-13 8:09 ` [Qemu-devel] [PATCH 1/2] target/i386: define a new MSR based feature word - FEAT_PERF_CAPABILITIES Like Xu
2020-06-13 8:09 ` Like Xu
2020-06-13 8:09 ` [Qemu-devel] [PATCH 2/2] target/i386: add -cpu,lbr=true support to enable guest LBR Like Xu
2020-06-13 8:09 ` [Qemu-devel] [PATCH 2/2] target/i386: add -cpu, lbr=true " Like Xu
2020-06-23 13:13 ` [PATCH v12 00/11] Guest Last Branch Recording Enabling Like Xu
2020-07-01 2:38 ` Like Xu
2020-07-02 7:40 ` Peter Zijlstra
2020-07-02 13:11 ` Liang, Kan
2020-07-02 13:58 ` Peter Zijlstra
2020-07-03 7:56 ` Peter Zijlstra
2020-07-03 8:04 ` Xu, Like
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