From: Claudiu Beznea <claudiu.beznea@microchip.com> To: <mturquette@baylibre.com>, <sboyd@kernel.org>, <nicolas.ferre@microchip.com>, <alexandre.belloni@bootlin.com>, <ludovic.desroches@microchip.com>, <robh+dt@kernel.org> Cc: <linux-clk@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, <linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>, Eugen Hristev <eugen.hristev@microchip.com>, Claudiu Beznea <claudiu.beznea@microchip.com> Subject: [PATCH v6 04/11] clk: at91: clk-master: add 5th divisor for mck master Date: Thu, 19 Nov 2020 17:43:10 +0200 [thread overview] Message-ID: <1605800597-16720-5-git-send-email-claudiu.beznea@microchip.com> (raw) In-Reply-To: <1605800597-16720-1-git-send-email-claudiu.beznea@microchip.com> From: Eugen Hristev <eugen.hristev@microchip.com> clk-master can have 5 divisors with a field width of 3 bits on some products. Change the mask and number of divisors accordingly. Reported-by: Mihai Sain <mihai.sain@microchip.com> Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> --- drivers/clk/at91/clk-master.c | 2 +- drivers/clk/at91/pmc.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/at91/clk-master.c b/drivers/clk/at91/clk-master.c index bd0d8a69a2cf..aafd003b30cf 100644 --- a/drivers/clk/at91/clk-master.c +++ b/drivers/clk/at91/clk-master.c @@ -15,7 +15,7 @@ #define MASTER_PRES_MASK 0x7 #define MASTER_PRES_MAX MASTER_PRES_MASK #define MASTER_DIV_SHIFT 8 -#define MASTER_DIV_MASK 0x3 +#define MASTER_DIV_MASK 0x7 #define PMC_MCR 0x30 #define PMC_MCR_ID_MSK GENMASK(3, 0) diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h index 7b86affc6d7c..0a9364bde339 100644 --- a/drivers/clk/at91/pmc.h +++ b/drivers/clk/at91/pmc.h @@ -48,7 +48,7 @@ extern const struct clk_master_layout at91sam9x5_master_layout; struct clk_master_characteristics { struct clk_range output; - u32 divisors[4]; + u32 divisors[5]; u8 have_div3_pres; }; -- 2.7.4
WARNING: multiple messages have this Message-ID (diff)
From: Claudiu Beznea <claudiu.beznea@microchip.com> To: <mturquette@baylibre.com>, <sboyd@kernel.org>, <nicolas.ferre@microchip.com>, <alexandre.belloni@bootlin.com>, <ludovic.desroches@microchip.com>, <robh+dt@kernel.org> Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Eugen Hristev <eugen.hristev@microchip.com>, Claudiu Beznea <claudiu.beznea@microchip.com>, linux-arm-kernel@lists.infradead.org Subject: [PATCH v6 04/11] clk: at91: clk-master: add 5th divisor for mck master Date: Thu, 19 Nov 2020 17:43:10 +0200 [thread overview] Message-ID: <1605800597-16720-5-git-send-email-claudiu.beznea@microchip.com> (raw) In-Reply-To: <1605800597-16720-1-git-send-email-claudiu.beznea@microchip.com> From: Eugen Hristev <eugen.hristev@microchip.com> clk-master can have 5 divisors with a field width of 3 bits on some products. Change the mask and number of divisors accordingly. Reported-by: Mihai Sain <mihai.sain@microchip.com> Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> --- drivers/clk/at91/clk-master.c | 2 +- drivers/clk/at91/pmc.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/at91/clk-master.c b/drivers/clk/at91/clk-master.c index bd0d8a69a2cf..aafd003b30cf 100644 --- a/drivers/clk/at91/clk-master.c +++ b/drivers/clk/at91/clk-master.c @@ -15,7 +15,7 @@ #define MASTER_PRES_MASK 0x7 #define MASTER_PRES_MAX MASTER_PRES_MASK #define MASTER_DIV_SHIFT 8 -#define MASTER_DIV_MASK 0x3 +#define MASTER_DIV_MASK 0x7 #define PMC_MCR 0x30 #define PMC_MCR_ID_MSK GENMASK(3, 0) diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h index 7b86affc6d7c..0a9364bde339 100644 --- a/drivers/clk/at91/pmc.h +++ b/drivers/clk/at91/pmc.h @@ -48,7 +48,7 @@ extern const struct clk_master_layout at91sam9x5_master_layout; struct clk_master_characteristics { struct clk_range output; - u32 divisors[4]; + u32 divisors[5]; u8 have_div3_pres; }; -- 2.7.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-11-19 15:44 UTC|newest] Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-11-19 15:43 [PATCH v6 00/11] clk: at91: clk-master: re-factor master clock Claudiu Beznea 2020-11-19 15:43 ` Claudiu Beznea 2020-11-19 15:43 ` [PATCH v6 01/11] clk: at91: sama7g5: fix compilation error Claudiu Beznea 2020-11-19 15:43 ` Claudiu Beznea 2020-12-19 19:53 ` Stephen Boyd 2020-12-19 19:53 ` Stephen Boyd 2020-11-19 15:43 ` [PATCH v6 02/11] dt-bindings: clock: at91: add sama7g5 pll defines Claudiu Beznea 2020-11-19 15:43 ` Claudiu Beznea 2020-12-19 19:53 ` Stephen Boyd 2020-12-19 19:53 ` Stephen Boyd 2020-11-19 15:43 ` [PATCH v6 03/11] clk: at91: sama7g5: allow SYS and CPU PLLs to be exported and referenced in DT Claudiu Beznea 2020-11-19 15:43 ` Claudiu Beznea 2020-12-19 19:53 ` Stephen Boyd 2020-12-19 19:53 ` Stephen Boyd 2020-11-19 15:43 ` Claudiu Beznea [this message] 2020-11-19 15:43 ` [PATCH v6 04/11] clk: at91: clk-master: add 5th divisor for mck master Claudiu Beznea 2020-12-19 19:53 ` Stephen Boyd 2020-12-19 19:53 ` Stephen Boyd 2020-11-19 15:43 ` [PATCH v6 05/11] clk: at91: sama7g5: add 5th divisor for mck0 layout and characteristics Claudiu Beznea 2020-11-19 15:43 ` Claudiu Beznea 2020-12-19 19:53 ` Stephen Boyd 2020-12-19 19:53 ` Stephen Boyd 2020-12-19 23:31 ` Stephen Boyd 2020-12-19 23:31 ` Stephen Boyd 2020-11-19 15:43 ` [PATCH v6 06/11] clk: at91: clk-sam9x60-pll: allow runtime changes for pll Claudiu Beznea 2020-11-19 15:43 ` Claudiu Beznea 2020-12-19 19:53 ` Stephen Boyd 2020-12-19 19:53 ` Stephen Boyd 2020-12-19 23:31 ` Stephen Boyd 2020-12-19 23:31 ` Stephen Boyd 2020-11-19 15:43 ` [PATCH v6 07/11] clk: at91: sama7g5: remove mck0 from parent list of other clocks Claudiu Beznea 2020-11-19 15:43 ` Claudiu Beznea 2020-12-19 23:32 ` Stephen Boyd 2020-12-19 23:32 ` Stephen Boyd 2020-11-19 15:43 ` [PATCH v6 08/11] clk: at91: sama7g5: decrease lower limit for MCK0 rate Claudiu Beznea 2020-11-19 15:43 ` Claudiu Beznea 2020-12-19 23:32 ` Stephen Boyd 2020-12-19 23:32 ` Stephen Boyd 2020-11-19 15:43 ` [PATCH v6 09/11] clk: at91: sama7g5: do not allow cpu pll to go higher than 1GHz Claudiu Beznea 2020-11-19 15:43 ` Claudiu Beznea 2020-12-19 23:32 ` Stephen Boyd 2020-12-19 23:32 ` Stephen Boyd 2020-11-19 15:43 ` [PATCH v6 10/11] clk: at91: clk-master: re-factor master clock Claudiu Beznea 2020-11-19 15:43 ` Claudiu Beznea 2020-12-19 23:32 ` Stephen Boyd 2020-12-19 23:32 ` Stephen Boyd 2020-11-19 15:43 ` [PATCH v6 11/11] clk: at91: sama7g5: register cpu clock Claudiu Beznea 2020-11-19 15:43 ` Claudiu Beznea 2020-12-19 23:32 ` Stephen Boyd 2020-12-19 23:32 ` Stephen Boyd 2020-11-27 12:12 ` [PATCH v6 00/11] clk: at91: clk-master: re-factor master clock Claudiu.Beznea 2020-11-27 12:12 ` Claudiu.Beznea
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