From: Stephen Boyd <sboyd@kernel.org>
To: Claudiu Beznea <claudiu.beznea@microchip.com>,
alexandre.belloni@bootlin.com, ludovic.desroches@microchip.com,
mturquette@baylibre.com, nicolas.ferre@microchip.com,
robh+dt@kernel.org
Cc: linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
Claudiu Beznea <claudiu.beznea@microchip.com>
Subject: Re: [PATCH v6 10/11] clk: at91: clk-master: re-factor master clock
Date: Sat, 19 Dec 2020 15:32:17 -0800 [thread overview]
Message-ID: <160842073774.1580929.9863083080209979336@swboyd.mtv.corp.google.com> (raw)
In-Reply-To: <1605800597-16720-11-git-send-email-claudiu.beznea@microchip.com>
Quoting Claudiu Beznea (2020-11-19 07:43:16)
> Re-factor master clock driver by splitting it into 2 clocks: prescaller
> and divider clocks. Based on registered clock flags the prescaler's rate
> could be changed at runtime. This is necessary for platforms supporting
> DVFS (e.g. SAMA7G5) where master clock could be changed at run-time.
>
> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
> ---
Applied to clk-next
WARNING: multiple messages have this Message-ID (diff)
From: Stephen Boyd <sboyd@kernel.org>
To: Claudiu Beznea <claudiu.beznea@microchip.com>,
alexandre.belloni@bootlin.com, ludovic.desroches@microchip.com,
mturquette@baylibre.com, nicolas.ferre@microchip.com,
robh+dt@kernel.org
Cc: devicetree@vger.kernel.org,
Claudiu Beznea <claudiu.beznea@microchip.com>,
linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v6 10/11] clk: at91: clk-master: re-factor master clock
Date: Sat, 19 Dec 2020 15:32:17 -0800 [thread overview]
Message-ID: <160842073774.1580929.9863083080209979336@swboyd.mtv.corp.google.com> (raw)
In-Reply-To: <1605800597-16720-11-git-send-email-claudiu.beznea@microchip.com>
Quoting Claudiu Beznea (2020-11-19 07:43:16)
> Re-factor master clock driver by splitting it into 2 clocks: prescaller
> and divider clocks. Based on registered clock flags the prescaler's rate
> could be changed at runtime. This is necessary for platforms supporting
> DVFS (e.g. SAMA7G5) where master clock could be changed at run-time.
>
> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
> ---
Applied to clk-next
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next prev parent reply other threads:[~2020-12-19 23:33 UTC|newest]
Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-19 15:43 [PATCH v6 00/11] clk: at91: clk-master: re-factor master clock Claudiu Beznea
2020-11-19 15:43 ` Claudiu Beznea
2020-11-19 15:43 ` [PATCH v6 01/11] clk: at91: sama7g5: fix compilation error Claudiu Beznea
2020-11-19 15:43 ` Claudiu Beznea
2020-12-19 19:53 ` Stephen Boyd
2020-12-19 19:53 ` Stephen Boyd
2020-11-19 15:43 ` [PATCH v6 02/11] dt-bindings: clock: at91: add sama7g5 pll defines Claudiu Beznea
2020-11-19 15:43 ` Claudiu Beznea
2020-12-19 19:53 ` Stephen Boyd
2020-12-19 19:53 ` Stephen Boyd
2020-11-19 15:43 ` [PATCH v6 03/11] clk: at91: sama7g5: allow SYS and CPU PLLs to be exported and referenced in DT Claudiu Beznea
2020-11-19 15:43 ` Claudiu Beznea
2020-12-19 19:53 ` Stephen Boyd
2020-12-19 19:53 ` Stephen Boyd
2020-11-19 15:43 ` [PATCH v6 04/11] clk: at91: clk-master: add 5th divisor for mck master Claudiu Beznea
2020-11-19 15:43 ` Claudiu Beznea
2020-12-19 19:53 ` Stephen Boyd
2020-12-19 19:53 ` Stephen Boyd
2020-11-19 15:43 ` [PATCH v6 05/11] clk: at91: sama7g5: add 5th divisor for mck0 layout and characteristics Claudiu Beznea
2020-11-19 15:43 ` Claudiu Beznea
2020-12-19 19:53 ` Stephen Boyd
2020-12-19 19:53 ` Stephen Boyd
2020-12-19 23:31 ` Stephen Boyd
2020-12-19 23:31 ` Stephen Boyd
2020-11-19 15:43 ` [PATCH v6 06/11] clk: at91: clk-sam9x60-pll: allow runtime changes for pll Claudiu Beznea
2020-11-19 15:43 ` Claudiu Beznea
2020-12-19 19:53 ` Stephen Boyd
2020-12-19 19:53 ` Stephen Boyd
2020-12-19 23:31 ` Stephen Boyd
2020-12-19 23:31 ` Stephen Boyd
2020-11-19 15:43 ` [PATCH v6 07/11] clk: at91: sama7g5: remove mck0 from parent list of other clocks Claudiu Beznea
2020-11-19 15:43 ` Claudiu Beznea
2020-12-19 23:32 ` Stephen Boyd
2020-12-19 23:32 ` Stephen Boyd
2020-11-19 15:43 ` [PATCH v6 08/11] clk: at91: sama7g5: decrease lower limit for MCK0 rate Claudiu Beznea
2020-11-19 15:43 ` Claudiu Beznea
2020-12-19 23:32 ` Stephen Boyd
2020-12-19 23:32 ` Stephen Boyd
2020-11-19 15:43 ` [PATCH v6 09/11] clk: at91: sama7g5: do not allow cpu pll to go higher than 1GHz Claudiu Beznea
2020-11-19 15:43 ` Claudiu Beznea
2020-12-19 23:32 ` Stephen Boyd
2020-12-19 23:32 ` Stephen Boyd
2020-11-19 15:43 ` [PATCH v6 10/11] clk: at91: clk-master: re-factor master clock Claudiu Beznea
2020-11-19 15:43 ` Claudiu Beznea
2020-12-19 23:32 ` Stephen Boyd [this message]
2020-12-19 23:32 ` Stephen Boyd
2020-11-19 15:43 ` [PATCH v6 11/11] clk: at91: sama7g5: register cpu clock Claudiu Beznea
2020-11-19 15:43 ` Claudiu Beznea
2020-12-19 23:32 ` Stephen Boyd
2020-12-19 23:32 ` Stephen Boyd
2020-11-27 12:12 ` [PATCH v6 00/11] clk: at91: clk-master: re-factor master clock Claudiu.Beznea
2020-11-27 12:12 ` Claudiu.Beznea
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