From: Russell King - ARM Linux <linux@arm.linux.org.uk>
To: Arnd Bergmann <arnd@arndb.de>
Cc: linux-arm-kernel@lists.infradead.org,
Sascha Hauer <s.hauer@pengutronix.de>,
Zhang Lily-R58066 <r58066@freescale.com>,
linux-fbdev@vger.kernel.org,
Arnaud Patard <arnaud.patard@rtp-net.org>,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH 1/9] ARM i.MX51: Add ipu clock support
Date: Wed, 15 Dec 2010 16:34:45 +0000 [thread overview]
Message-ID: <20101215163445.GE9937@n2100.arm.linux.org.uk> (raw)
In-Reply-To: <201012151640.03789.arnd@arndb.de>
On Wed, Dec 15, 2010 at 04:40:03PM +0100, Arnd Bergmann wrote:
> On Thursday 09 December 2010, Sascha Hauer wrote:
> > +static int clk_ipu_enable(struct clk *clk)
> > +{
> > + u32 reg;
> > +
> > + _clk_ccgr_enable(clk);
> > +
> > + /* Enable handshake with IPU when certain clock rates are changed */
> > + reg = __raw_readl(MXC_CCM_CCDR);
> > + reg &= ~MXC_CCM_CCDR_IPU_HS_MASK;
> > + __raw_writel(reg, MXC_CCM_CCDR);
> > +
> > + /* Enable handshake with IPU when LPM is entered */
> > + reg = __raw_readl(MXC_CCM_CLPCR);
> > + reg &= ~MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS;
> > + __raw_writel(reg, MXC_CCM_CLPCR);
> > +
> > + return 0;
> > +}
>
> Why __raw_readl?
>
> The regular accessor function for I/O registers is readl, which handles
> the access correctly with regard to atomicity, I/O ordering and byteorder.
There's no possibility of those two being mis-ordered - they will be in
program order whatever.
What isn't guaranteed is the ordering between I/O accesses (accesses to
device memory) and SDRAM accesses (normal memory) which can pass each other
without additional barriers. Memory accesses can pass I/O accesses.
So, (eg), if you're writing to a register which causes the hardware to
begin reading DMA descriptors from an area allocated from dma_alloc_coherent(),
you need a barrier to ensure that writes to the dma_alloc_coherent() are
visible to the hardware before you write the enable register.
If you don't need normal vs device access ordering, using readl_relaxed()/
writel_relaxed() is preferred, and avoids the (apparantly rather high)
performance overhead of having to issue barriers all the way down to the
L2 cache.
Lastly, I don't see where atomicity comes into it - __raw_writel vs writel
have the same atomicity. Both are single access atomic provided they're
naturally aligned. Misaligned device accesses are not predictable.
WARNING: multiple messages have this Message-ID (diff)
From: Russell King - ARM Linux <linux@arm.linux.org.uk>
To: linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 1/9] ARM i.MX51: Add ipu clock support
Date: Wed, 15 Dec 2010 16:34:45 +0000 [thread overview]
Message-ID: <20101215163445.GE9937@n2100.arm.linux.org.uk> (raw)
In-Reply-To: <201012151640.03789.arnd@arndb.de>
On Wed, Dec 15, 2010 at 04:40:03PM +0100, Arnd Bergmann wrote:
> On Thursday 09 December 2010, Sascha Hauer wrote:
> > +static int clk_ipu_enable(struct clk *clk)
> > +{
> > + u32 reg;
> > +
> > + _clk_ccgr_enable(clk);
> > +
> > + /* Enable handshake with IPU when certain clock rates are changed */
> > + reg = __raw_readl(MXC_CCM_CCDR);
> > + reg &= ~MXC_CCM_CCDR_IPU_HS_MASK;
> > + __raw_writel(reg, MXC_CCM_CCDR);
> > +
> > + /* Enable handshake with IPU when LPM is entered */
> > + reg = __raw_readl(MXC_CCM_CLPCR);
> > + reg &= ~MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS;
> > + __raw_writel(reg, MXC_CCM_CLPCR);
> > +
> > + return 0;
> > +}
>
> Why __raw_readl?
>
> The regular accessor function for I/O registers is readl, which handles
> the access correctly with regard to atomicity, I/O ordering and byteorder.
There's no possibility of those two being mis-ordered - they will be in
program order whatever.
What isn't guaranteed is the ordering between I/O accesses (accesses to
device memory) and SDRAM accesses (normal memory) which can pass each other
without additional barriers. Memory accesses can pass I/O accesses.
So, (eg), if you're writing to a register which causes the hardware to
begin reading DMA descriptors from an area allocated from dma_alloc_coherent(),
you need a barrier to ensure that writes to the dma_alloc_coherent() are
visible to the hardware before you write the enable register.
If you don't need normal vs device access ordering, using readl_relaxed()/
writel_relaxed() is preferred, and avoids the (apparantly rather high)
performance overhead of having to issue barriers all the way down to the
L2 cache.
Lastly, I don't see where atomicity comes into it - __raw_writel vs writel
have the same atomicity. Both are single access atomic provided they're
naturally aligned. Misaligned device accesses are not predictable.
WARNING: multiple messages have this Message-ID (diff)
From: linux@arm.linux.org.uk (Russell King - ARM Linux)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 1/9] ARM i.MX51: Add ipu clock support
Date: Wed, 15 Dec 2010 16:34:45 +0000 [thread overview]
Message-ID: <20101215163445.GE9937@n2100.arm.linux.org.uk> (raw)
In-Reply-To: <201012151640.03789.arnd@arndb.de>
On Wed, Dec 15, 2010 at 04:40:03PM +0100, Arnd Bergmann wrote:
> On Thursday 09 December 2010, Sascha Hauer wrote:
> > +static int clk_ipu_enable(struct clk *clk)
> > +{
> > + u32 reg;
> > +
> > + _clk_ccgr_enable(clk);
> > +
> > + /* Enable handshake with IPU when certain clock rates are changed */
> > + reg = __raw_readl(MXC_CCM_CCDR);
> > + reg &= ~MXC_CCM_CCDR_IPU_HS_MASK;
> > + __raw_writel(reg, MXC_CCM_CCDR);
> > +
> > + /* Enable handshake with IPU when LPM is entered */
> > + reg = __raw_readl(MXC_CCM_CLPCR);
> > + reg &= ~MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS;
> > + __raw_writel(reg, MXC_CCM_CLPCR);
> > +
> > + return 0;
> > +}
>
> Why __raw_readl?
>
> The regular accessor function for I/O registers is readl, which handles
> the access correctly with regard to atomicity, I/O ordering and byteorder.
There's no possibility of those two being mis-ordered - they will be in
program order whatever.
What isn't guaranteed is the ordering between I/O accesses (accesses to
device memory) and SDRAM accesses (normal memory) which can pass each other
without additional barriers. Memory accesses can pass I/O accesses.
So, (eg), if you're writing to a register which causes the hardware to
begin reading DMA descriptors from an area allocated from dma_alloc_coherent(),
you need a barrier to ensure that writes to the dma_alloc_coherent() are
visible to the hardware before you write the enable register.
If you don't need normal vs device access ordering, using readl_relaxed()/
writel_relaxed() is preferred, and avoids the (apparantly rather high)
performance overhead of having to issue barriers all the way down to the
L2 cache.
Lastly, I don't see where atomicity comes into it - __raw_writel vs writel
have the same atomicity. Both are single access atomic provided they're
naturally aligned. Misaligned device accesses are not predictable.
next prev parent reply other threads:[~2010-12-15 16:35 UTC|newest]
Thread overview: 110+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-12-09 13:47 [PATCH RFC] i.MX51 Framebuffer support Sascha Hauer
2010-12-09 13:47 ` Sascha Hauer
2010-12-09 13:47 ` Sascha Hauer
2010-12-09 13:47 ` [PATCH 1/9] ARM i.MX51: Add ipu clock support Sascha Hauer
2010-12-09 13:47 ` Sascha Hauer
2010-12-09 13:47 ` Sascha Hauer
2010-12-15 15:40 ` Arnd Bergmann
2010-12-15 15:40 ` Arnd Bergmann
2010-12-15 15:40 ` Arnd Bergmann
2010-12-15 16:34 ` Russell King - ARM Linux [this message]
2010-12-15 16:34 ` Russell King - ARM Linux
2010-12-15 16:34 ` Russell King - ARM Linux
2010-12-15 16:49 ` Arnd Bergmann
2010-12-15 16:49 ` Arnd Bergmann
2010-12-15 16:49 ` Arnd Bergmann
2010-12-15 17:12 ` Russell King - ARM Linux
2010-12-15 17:12 ` Russell King - ARM Linux
2010-12-15 17:12 ` Russell King - ARM Linux
2010-12-09 13:47 ` [PATCH 2/9] ARM i.MX51: rename IPU irqs Sascha Hauer
2010-12-09 13:47 ` Sascha Hauer
2010-12-09 13:47 ` Sascha Hauer
2010-12-09 14:34 ` Uwe Kleine-König
2010-12-09 14:34 ` Uwe Kleine-König
2010-12-09 14:34 `
2010-12-09 13:47 ` [PATCH 3/9] Add a mfd IPUv3 driver Sascha Hauer
2010-12-09 13:47 ` Sascha Hauer
2010-12-12 5:21 ` Liu Ying
2010-12-12 5:21 ` Liu Ying
2010-12-13 11:23 ` Sascha Hauer
2010-12-13 11:23 ` Sascha Hauer
2010-12-13 11:23 ` Sascha Hauer
2010-12-14 4:05 ` Liu Ying
2010-12-14 4:05 ` Liu Ying
2010-12-14 4:05 ` Liu Ying
2010-12-14 8:40 ` Sascha Hauer
2010-12-14 8:40 ` Sascha Hauer
2010-12-14 8:40 ` Sascha Hauer
2010-12-14 13:13 ` Liu Ying
2010-12-14 13:13 ` Liu Ying
2010-12-14 13:13 ` Liu Ying
2010-12-09 13:47 ` [PATCH 4/9] fb: export fb mode db table Sascha Hauer
2010-12-09 13:47 ` Sascha Hauer
2010-12-09 13:47 ` Sascha Hauer
2011-01-06 7:26 ` Paul Mundt
2011-01-06 7:26 ` Paul Mundt
2011-01-06 7:26 ` Paul Mundt
2011-01-06 10:04 ` Sascha Hauer
2011-01-06 10:04 ` Sascha Hauer
2011-01-06 10:04 ` Sascha Hauer
2010-12-09 13:47 ` [PATCH 5/9] Add i.MX5 framebuffer driver Sascha Hauer
2010-12-09 13:47 ` Sascha Hauer
2010-12-09 13:47 ` Sascha Hauer
2010-12-12 6:13 ` Liu Ying
2010-12-12 6:13 ` Liu Ying
2010-12-12 6:13 ` Liu Ying
2010-12-13 7:23 ` Lothar Waßmann
2010-12-13 7:23 ` Lothar Waßmann
2010-12-13 7:23 ` Lothar Waßmann
2010-12-13 11:35 ` Liu Ying
2010-12-13 11:35 ` Liu Ying
2010-12-13 11:35 ` Liu Ying
2010-12-13 11:38 ` Sascha Hauer
2010-12-13 11:38 ` Sascha Hauer
2010-12-13 11:38 ` Sascha Hauer
2010-12-14 6:40 ` Liu Ying
2010-12-14 6:40 ` Liu Ying
2010-12-14 6:40 ` Liu Ying
2010-12-14 8:45 ` Sascha Hauer
2010-12-14 8:45 ` Sascha Hauer
2010-12-14 8:45 ` Sascha Hauer
2010-12-14 13:23 ` Liu Ying
2010-12-14 13:23 ` Liu Ying
2010-12-14 13:23 ` Liu Ying
2010-12-15 11:17 ` Sascha Hauer
2010-12-15 11:17 ` Sascha Hauer
2010-12-15 11:17 ` Sascha Hauer
2010-12-09 13:47 ` [PATCH 6/9] ARM i.MX51: Add IPU device support Sascha Hauer
2010-12-09 13:47 ` Sascha Hauer
2010-12-09 13:47 ` Sascha Hauer
2010-12-15 15:49 ` Arnd Bergmann
2010-12-15 15:49 ` Arnd Bergmann
2010-12-15 15:49 ` Arnd Bergmann
2010-12-15 16:26 ` Arnaud Patard
2010-12-15 16:26 ` Arnaud Patard (Rtp)
2010-12-15 16:26 ` Arnaud Patard
2010-12-15 16:29 ` Arnd Bergmann
2010-12-15 16:29 ` Arnd Bergmann
2010-12-15 16:29 ` Arnd Bergmann
2010-12-09 13:47 ` [PATCH 7/9] ARM i.MX5: Allow to increase max zone order Sascha Hauer
2010-12-09 13:47 ` Sascha Hauer
2010-12-09 13:47 ` Sascha Hauer
2010-12-09 13:47 ` [PATCH 8/9] ARM i.MX5: increase dma consistent size for IPU support Sascha Hauer
2010-12-09 13:47 ` Sascha Hauer
2010-12-09 13:47 ` Sascha Hauer
2010-12-09 13:47 ` [PATCH 9/9] ARM i.MX51 babbage: Add framebuffer support Sascha Hauer
2010-12-09 13:47 ` Sascha Hauer
2010-12-09 13:47 ` Sascha Hauer
2010-12-12 1:37 ` Liu Ying
2010-12-12 1:37 ` Liu Ying
2010-12-12 1:37 ` Liu Ying
2010-12-13 11:43 ` Sascha Hauer
2010-12-13 11:43 ` Sascha Hauer
2010-12-13 11:43 ` Sascha Hauer
2010-12-14 6:47 ` Liu Ying
2010-12-14 6:47 ` Liu Ying
2010-12-14 6:47 ` Liu Ying
2010-12-15 9:35 ` [PATCH RFC] i.MX51 Framebuffer support Peter Horton
2010-12-15 11:24 ` Sascha Hauer
2010-12-20 10:48 [PATCH v2] " Sascha Hauer
2010-12-20 10:48 ` [PATCH 1/9] ARM i.MX51: Add ipu clock support Sascha Hauer
2010-12-20 10:48 ` Sascha Hauer
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