From: Andrew Lunn <andrew-g2DYL2Zd6BY@public.gmane.org> To: Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org> Cc: Andrew Lunn <andrew-g2DYL2Zd6BY@public.gmane.org>, Sebastian Hesselbarth <sebastian.hesselbarth-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, Jason Cooper <jason-NLaQJdtUoK4Be96aLqz0jA@public.gmane.org>, devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org, rob.herring-bsGFqQB8/DxBDgjK7y7TUQ@public.gmane.org, grant.likely-s3s/WqlpOiPyB63q8FvJNQ@public.gmane.org, Michael Walle <michael-QKn5cuLxLXY@public.gmane.org>, linux-i2c-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, spi-devel-general-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org Subject: Re: [PATCH v2 01/12] ARM: Orion: DT support for IRQ and GPIO Controllers Date: Fri, 6 Jul 2012 23:00:09 +0200 [thread overview] Message-ID: <20120706210009.GC11470@lunn.ch> (raw) In-Reply-To: <201207062008.23952.arnd-r2nGTMty4D4@public.gmane.org> On Fri, Jul 06, 2012 at 08:08:23PM +0000, Arnd Bergmann wrote: > On Thursday 05 July 2012, Andrew Lunn wrote: > > > I think the latter one needs to be > > > > > > +static int __initdata gpio1_irqs[4] = { > > > + IRQ_DOVE_HIGH_GPIO, > > > + IRQ_DOVE_HIGH_GPIO, > > > + IRQ_DOVE_HIGH_GPIO, > > > + IRQ_DOVE_HIGH_GPIO, > > > +}; > > > > > > so we register all four parts to the same primary IRQ. The > > > same is true for the devicetree representation. > > > > Nope, does not work like that. > > > > It does not matter which IRQ of a GPIO chip fires. It looks at the IRQ > > cause bits for all lines and fires off the secondary ISR as needed for > > the whole chip. So in effect, there is a mapping IRQ->GPIO chip, not > > IRQ->1/4 of GPIO chip. With what you suggest above, you would end up > > with four chained interrupt handlers, all being handled by the same > > interrupt handler for one chio, and the last three in the chain would > > never do anything since the first one does all the work. > > Does it really? > > The handler function I'm looking at is > > > static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) > { > int irqoff; > BUG_ON(irq < IRQ_DOVE_GPIO_0_7 || irq > IRQ_DOVE_HIGH_GPIO); > > irqoff = irq <= IRQ_DOVE_GPIO_16_23 ? irq - IRQ_DOVE_GPIO_0_7 : > 3 + irq - IRQ_DOVE_GPIO_24_31; > > orion_gpio_irq_handler(irqoff << 3); > if (irq == IRQ_DOVE_HIGH_GPIO) { > orion_gpio_irq_handler(40); > orion_gpio_irq_handler(48); > orion_gpio_irq_handler(56); > } > } void orion_gpio_irq_handler(int pinoff) { struct orion_gpio_chip *ochip; u32 cause, type; int i; ochip = orion_gpio_chip_find(pinoff); if (ochip == NULL) return; cause = readl(GPIO_DATA_IN(ochip)) & readl(GPIO_LEVEL_MASK(ochip)); cause |= readl(GPIO_EDGE_CAUSE(ochip)) & readl(GPIO_EDGE_MASK(ochip)); for (i = 0; i < ochip->chip.ngpio; i++) { int irq; irq = ochip->secondary_irq_base + i; if (!(cause & (1 << i))) continue; type = irqd_get_trigger_type(irq_get_irq_data(irq)); if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) { /* Swap polarity (race with GPIO line) */ u32 polarity; polarity = readl(GPIO_IN_POL(ochip)); polarity ^= 1 << i; writel(polarity, GPIO_IN_POL(ochip)); } generic_handle_irq(irq); } } orion_gpio_chip_find(pinoff) when called with pinoff 32, 40, 48, or 56 will return the same gpio chip. The loop: for (i = 0; i < ochip->chip.ngpio; i++) { will iterate over all lines of the controller. > My reading of this is a manual hardwired implementation of a > primary handler that triggers the secondary handler four times > when it's called with a specific argument. Here is your mistake. It not a secondary handler. It is a function which might trigger a secondary handler, if the status bit requires that the secondary handler should be called.. > If you want to keep that behavior, this handler cannot be > generic across all mvebu socs, whereas registering four > chained handlers for the same primary interrupt would have > the same effect at a very small runtime overhead without the > need for any special case. I would say the current code does redundant stuff. This code has also been tested on a Dove by Sebastian Hesselbarth and he did not notice anything strange happening on his system. Andrew
WARNING: multiple messages have this Message-ID (diff)
From: andrew@lunn.ch (Andrew Lunn) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 01/12] ARM: Orion: DT support for IRQ and GPIO Controllers Date: Fri, 6 Jul 2012 23:00:09 +0200 [thread overview] Message-ID: <20120706210009.GC11470@lunn.ch> (raw) In-Reply-To: <201207062008.23952.arnd@arndb.de> On Fri, Jul 06, 2012 at 08:08:23PM +0000, Arnd Bergmann wrote: > On Thursday 05 July 2012, Andrew Lunn wrote: > > > I think the latter one needs to be > > > > > > +static int __initdata gpio1_irqs[4] = { > > > + IRQ_DOVE_HIGH_GPIO, > > > + IRQ_DOVE_HIGH_GPIO, > > > + IRQ_DOVE_HIGH_GPIO, > > > + IRQ_DOVE_HIGH_GPIO, > > > +}; > > > > > > so we register all four parts to the same primary IRQ. The > > > same is true for the devicetree representation. > > > > Nope, does not work like that. > > > > It does not matter which IRQ of a GPIO chip fires. It looks at the IRQ > > cause bits for all lines and fires off the secondary ISR as needed for > > the whole chip. So in effect, there is a mapping IRQ->GPIO chip, not > > IRQ->1/4 of GPIO chip. With what you suggest above, you would end up > > with four chained interrupt handlers, all being handled by the same > > interrupt handler for one chio, and the last three in the chain would > > never do anything since the first one does all the work. > > Does it really? > > The handler function I'm looking at is > > > static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) > { > int irqoff; > BUG_ON(irq < IRQ_DOVE_GPIO_0_7 || irq > IRQ_DOVE_HIGH_GPIO); > > irqoff = irq <= IRQ_DOVE_GPIO_16_23 ? irq - IRQ_DOVE_GPIO_0_7 : > 3 + irq - IRQ_DOVE_GPIO_24_31; > > orion_gpio_irq_handler(irqoff << 3); > if (irq == IRQ_DOVE_HIGH_GPIO) { > orion_gpio_irq_handler(40); > orion_gpio_irq_handler(48); > orion_gpio_irq_handler(56); > } > } void orion_gpio_irq_handler(int pinoff) { struct orion_gpio_chip *ochip; u32 cause, type; int i; ochip = orion_gpio_chip_find(pinoff); if (ochip == NULL) return; cause = readl(GPIO_DATA_IN(ochip)) & readl(GPIO_LEVEL_MASK(ochip)); cause |= readl(GPIO_EDGE_CAUSE(ochip)) & readl(GPIO_EDGE_MASK(ochip)); for (i = 0; i < ochip->chip.ngpio; i++) { int irq; irq = ochip->secondary_irq_base + i; if (!(cause & (1 << i))) continue; type = irqd_get_trigger_type(irq_get_irq_data(irq)); if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) { /* Swap polarity (race with GPIO line) */ u32 polarity; polarity = readl(GPIO_IN_POL(ochip)); polarity ^= 1 << i; writel(polarity, GPIO_IN_POL(ochip)); } generic_handle_irq(irq); } } orion_gpio_chip_find(pinoff) when called with pinoff 32, 40, 48, or 56 will return the same gpio chip. The loop: for (i = 0; i < ochip->chip.ngpio; i++) { will iterate over all lines of the controller. > My reading of this is a manual hardwired implementation of a > primary handler that triggers the secondary handler four times > when it's called with a specific argument. Here is your mistake. It not a secondary handler. It is a function which might trigger a secondary handler, if the status bit requires that the secondary handler should be called.. > If you want to keep that behavior, this handler cannot be > generic across all mvebu socs, whereas registering four > chained handlers for the same primary interrupt would have > the same effect at a very small runtime overhead without the > need for any special case. I would say the current code does redundant stuff. This code has also been tested on a Dove by Sebastian Hesselbarth and he did not notice anything strange happening on his system. Andrew
next prev parent reply other threads:[~2012-07-06 21:00 UTC|newest] Thread overview: 130+ messages / expand[flat|nested] mbox.gz Atom feed top 2012-07-03 14:22 [PATCH v2 00/12] IRQ, GPIO SPI, I2C, etc DTC support Andrew Lunn 2012-07-03 14:22 ` Andrew Lunn [not found] ` <1341325365-21393-1-git-send-email-andrew-g2DYL2Zd6BY@public.gmane.org> 2012-07-03 14:22 ` [PATCH v2 01/12] ARM: Orion: DT support for IRQ and GPIO Controllers Andrew Lunn 2012-07-03 14:22 ` Andrew Lunn 2012-07-05 8:15 ` Andrew Lunn [not found] ` <1341325365-21393-2-git-send-email-andrew-g2DYL2Zd6BY@public.gmane.org> 2012-07-05 9:02 ` Thomas Petazzoni 2012-07-05 9:02 ` Thomas Petazzoni 2012-07-05 9:48 ` Andrew Lunn 2012-07-05 9:48 ` Andrew Lunn 2012-07-05 10:11 ` Arnaud Patard 2012-07-05 10:11 ` Arnaud Patard (Rtp) [not found] ` <87sjd6ikkj.fsf-0gaJ4kiyQU6khWr4QmshqB2eb7JE58TQ@public.gmane.org> 2012-07-05 10:20 ` Thomas Petazzoni 2012-07-05 10:20 ` Thomas Petazzoni 2012-07-05 10:38 ` Arnaud Patard 2012-07-05 10:38 ` Arnaud Patard (Rtp) [not found] ` <87liiyijb8.fsf-0gaJ4kiyQU6khWr4QmshqB2eb7JE58TQ@public.gmane.org> 2012-07-05 11:42 ` Thomas Petazzoni 2012-07-05 11:42 ` Thomas Petazzoni 2012-07-05 11:48 ` Andrew Lunn 2012-07-05 11:48 ` Andrew Lunn [not found] ` <20120705114815.GT17534-g2DYL2Zd6BY@public.gmane.org> 2012-07-05 12:09 ` Sebastian Hesselbarth 2012-07-05 12:09 ` Sebastian Hesselbarth [not found] ` <20120705094824.GO17534-g2DYL2Zd6BY@public.gmane.org> 2012-07-05 10:10 ` Thomas Petazzoni 2012-07-05 10:10 ` Thomas Petazzoni 2012-07-05 10:25 ` Andrew Lunn 2012-07-05 10:25 ` Andrew Lunn 2012-07-05 12:58 ` Thomas Petazzoni 2012-07-05 12:58 ` Thomas Petazzoni 2012-07-05 13:15 ` Andrew Lunn 2012-07-05 13:15 ` Andrew Lunn [not found] ` <20120705131522.GW17534-g2DYL2Zd6BY@public.gmane.org> 2012-07-05 13:28 ` Thomas Petazzoni 2012-07-05 13:28 ` Thomas Petazzoni 2012-07-05 13:33 ` Andrew Lunn 2012-07-05 13:36 ` Thomas Petazzoni 2012-07-05 12:25 ` Arnd Bergmann 2012-07-05 12:25 ` Arnd Bergmann [not found] ` <201207051225.55390.arnd-r2nGTMty4D4@public.gmane.org> 2012-07-05 13:08 ` Andrew Lunn 2012-07-05 13:08 ` Andrew Lunn [not found] ` <20120705130819.GV17534-g2DYL2Zd6BY@public.gmane.org> 2012-07-05 13:47 ` Arnd Bergmann 2012-07-05 13:47 ` Arnd Bergmann [not found] ` <201207051347.38887.arnd-r2nGTMty4D4@public.gmane.org> 2012-07-05 13:54 ` Andrew Lunn 2012-07-05 13:54 ` Andrew Lunn [not found] ` <20120705135449.GZ17534-g2DYL2Zd6BY@public.gmane.org> 2012-07-05 15:47 ` Arnd Bergmann 2012-07-05 15:47 ` Arnd Bergmann 2012-07-05 14:14 ` Sebastian Hesselbarth 2012-07-05 14:14 ` Sebastian Hesselbarth [not found] ` <4FF5A15A.8070309-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org> 2012-07-05 14:43 ` Andrew Lunn 2012-07-05 14:43 ` Andrew Lunn 2012-07-05 14:54 ` Arnd Bergmann 2012-07-05 14:54 ` Arnd Bergmann [not found] ` <201207051454.24475.arnd-r2nGTMty4D4@public.gmane.org> 2012-07-05 15:51 ` Sebastian Hesselbarth 2012-07-05 15:51 ` Sebastian Hesselbarth [not found] ` <4FF5B7F9.9020507-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org> 2012-07-05 16:30 ` Arnaud Patard 2012-07-05 16:30 ` Arnaud Patard (Rtp) 2012-07-05 16:16 ` Andrew Lunn 2012-07-05 16:16 ` Andrew Lunn [not found] ` <20120705161600.GA28860-g2DYL2Zd6BY@public.gmane.org> 2012-07-06 20:08 ` Arnd Bergmann 2012-07-06 20:08 ` Arnd Bergmann [not found] ` <201207062008.23952.arnd-r2nGTMty4D4@public.gmane.org> 2012-07-06 21:00 ` Andrew Lunn [this message] 2012-07-06 21:00 ` Andrew Lunn [not found] ` <20120706210009.GC11470-g2DYL2Zd6BY@public.gmane.org> 2012-07-07 0:24 ` Where to put a large bootloader-supplied device tree on ARM ? Mitch Bradley 2012-07-07 0:24 ` Mitch Bradley [not found] ` <4FF781D8.3040206-D5eQfiDGL7eakBO8gow8eQ@public.gmane.org> 2012-07-07 1:23 ` David VomLehn (dvomlehn) 2012-07-07 1:23 ` David VomLehn (dvomlehn) [not found] ` <2966DB01BC317A4DA23684BA0F653415013701-WE/xwOPrfQKHONfmNwMhBaBKnGwkPULj@public.gmane.org> 2012-07-07 1:59 ` Mitch Bradley 2012-07-07 1:59 ` Mitch Bradley [not found] ` <4FF7980E.7050705-D5eQfiDGL7eakBO8gow8eQ@public.gmane.org> 2012-07-09 4:30 ` Nicolas Pitre 2012-07-09 4:30 ` Nicolas Pitre [not found] ` <alpine.LFD.2.02.1207090015270.31100-QuJgVwGFrdf/9pzu0YdTqQ@public.gmane.org> 2012-07-12 6:52 ` Mitch Bradley 2012-07-12 6:52 ` Mitch Bradley [not found] ` <4FFE743B.6080504-D5eQfiDGL7eakBO8gow8eQ@public.gmane.org> 2012-07-12 18:16 ` Nicolas Pitre 2012-07-12 18:16 ` Nicolas Pitre 2012-07-12 20:34 ` Rob Herring 2012-07-12 20:34 ` [U-Boot] " Rob Herring 2012-07-12 20:34 ` Rob Herring 2012-07-12 21:38 ` Albert ARIBAUD 2012-07-12 21:38 ` [U-Boot] " Albert ARIBAUD 2012-07-12 21:38 ` Albert ARIBAUD 2012-07-12 21:47 ` Wolfgang Denk 2012-07-12 21:47 ` [U-Boot] " Wolfgang Denk 2012-07-12 21:47 ` Wolfgang Denk 2012-07-13 1:28 ` Rob Herring 2012-07-13 1:28 ` [U-Boot] " Rob Herring 2012-07-13 1:28 ` Rob Herring [not found] ` <4FFF79B6.6040508-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> 2012-07-13 6:45 ` Albert ARIBAUD 2012-07-13 6:45 ` Albert ARIBAUD 2012-07-13 6:45 ` Albert ARIBAUD 2012-07-05 18:36 ` [PATCH v2 01/12] ARM: Orion: DT support for IRQ and GPIO Controllers Mitch Bradley 2012-07-05 18:36 ` Mitch Bradley 2012-07-03 14:22 ` [PATCH v2 02/12] SPI: Refactor spi-orion to use SPI framework queue Andrew Lunn 2012-07-03 14:22 ` Andrew Lunn 2012-07-03 14:22 ` [PATCH v2 03/12] spi-orion: remove uneeded spi_info Andrew Lunn 2012-07-03 14:22 ` Andrew Lunn 2012-07-03 14:22 ` [PATCH v2 04/12] spi-orion: add device tree binding Andrew Lunn 2012-07-03 14:22 ` Andrew Lunn 2012-07-03 14:22 ` [PATCH v2 05/12] ARM: kirkwood: use devicetree for orion-spi Andrew Lunn 2012-07-03 14:22 ` Andrew Lunn 2012-07-03 14:22 ` [PATCH v2 06/12] ARM: kirkwood: use devicetree for SPI on dreamplug Andrew Lunn 2012-07-03 14:22 ` Andrew Lunn 2012-07-03 14:22 ` [PATCH v2 07/12] I2C: MV64XXX: Add Device Tree support Andrew Lunn 2012-07-03 14:22 ` Andrew Lunn [not found] ` <1341325365-21393-8-git-send-email-andrew-g2DYL2Zd6BY@public.gmane.org> 2012-07-03 15:59 ` Florian Fainelli 2012-07-03 15:59 ` Florian Fainelli 2012-07-03 16:58 ` Andrew Lunn 2012-07-03 16:58 ` Andrew Lunn [not found] ` <20120703165839.GA1519-g2DYL2Zd6BY@public.gmane.org> 2012-07-04 19:49 ` Florian Fainelli 2012-07-04 19:49 ` Florian Fainelli 2012-07-05 6:52 ` Andrew Lunn 2012-07-05 6:52 ` Andrew Lunn 2012-07-03 14:22 ` [PATCH v2 08/12] Kirkwood: Add basic device tree support for QNAP TS219 Andrew Lunn 2012-07-03 14:22 ` Andrew Lunn [not found] ` <1341325365-21393-9-git-send-email-andrew-g2DYL2Zd6BY@public.gmane.org> 2012-07-03 15:47 ` Florian Fainelli 2012-07-03 15:47 ` Florian Fainelli 2012-07-03 17:09 ` Andrew Lunn 2012-07-03 17:09 ` Andrew Lunn 2012-07-03 14:22 ` [PATCH v2 09/12] ARM: Kirkwood: DTify the watchdog timer Andrew Lunn 2012-07-03 14:22 ` Andrew Lunn 2012-07-03 14:22 ` [PATCH v2 10/12] ATA: sata_mv: Add device tree support Andrew Lunn 2012-07-03 14:22 ` Andrew Lunn 2012-07-03 14:22 ` [PATCH v2 11/12] ARM: Kirkwood: Use DT to configure SATA device Andrew Lunn 2012-07-03 14:22 ` Andrew Lunn [not found] ` <1341325365-21393-12-git-send-email-andrew-g2DYL2Zd6BY@public.gmane.org> 2012-07-03 14:52 ` Josh Coombs 2012-07-03 14:52 ` Josh Coombs [not found] ` <CAMW5Ufa2bsYs9VD2g9hJWKpcQNcZt+WXCA1ohYoHeLk9SambSg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> 2012-07-03 15:32 ` Andrew Lunn 2012-07-03 15:32 ` Andrew Lunn 2012-07-03 14:22 ` [PATCH v2 12/12] Crypto: CESA: Add support for DT based instantiation Andrew Lunn 2012-07-03 14:22 ` Andrew Lunn [not found] ` <1341325365-21393-13-git-send-email-andrew-g2DYL2Zd6BY@public.gmane.org> 2012-07-03 15:50 ` Florian Fainelli 2012-07-03 15:50 ` Florian Fainelli 2012-07-03 17:03 ` Andrew Lunn 2012-07-03 17:03 ` Andrew Lunn
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