From: Josh Cartwright <joshc-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
To: Bjorn Andersson <bjorn-UYDU3/A3LUY@public.gmane.org>
Cc: Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>,
Grant Likely
<grant.likely-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>,
Rob Herring <rob.herring-bsGFqQB8/DxBDgjK7y7TUQ@public.gmane.org>,
Greg Kroah-Hartman
<gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r@public.gmane.org>,
Pawel Moll <pawel.moll-5wv7dgnIgG8@public.gmane.org>,
Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>,
Ian Campbell
<ian.campbell-Sxgqhf6Nn4DQT0dZR+AlfA@public.gmane.org>,
Kumar Gala <galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Sagar Dharia <sdharia-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>,
Gilad Avidov <gavidov-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>,
Michael Bohan <mbohan-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Subject: Re: [PATCH RFC v2 3/5] spmi: add generic SPMI controller binding documentation
Date: Mon, 7 Oct 2013 16:17:56 -0500 [thread overview]
Message-ID: <20131007211756.GA1036@joshc.qualcomm.com> (raw)
In-Reply-To: <CAJAp7Oi-bPytsLtsppdanOi_p0Y5vfBriGB-B5by7w5Z7SGU-Q-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
Hey Bjorn-
On Sat, Oct 05, 2013 at 11:11:36PM -0700, Bjorn Andersson wrote:
> On Tue, Aug 27, 2013 at 2:55 PM, Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> wrote:
> > On 08/27/2013 11:01 AM, Josh Cartwright wrote:
> > ...
> > cell 0 - address type (0: master, 1: unique ID, 2: group ID, ...)
>
> I think it would make sense to have the master id as a property of the
> bus,
Except that SPMI supports bus configurations with multiple masters.
Unless by 'bus' you meant 'bus controller' here?
> as you could consider this to indicate different buses and then
> usid, gsid and base being part of the reg.
>
> > cell 1 - address value
>
> I did hack up Josh patchset to read a reg touple of <usid, base>
> instead of just usid. I stored the second value in the spmi_device
> struct for easy access, but maybe it should be done like on
> codeaurora; in a resource?
> I believe this looks nice, but as I haven't read the mipi spec I
> wonder, will there be a case where you don't have an offset/base?
> Should it just be made optional?
The SPMI spec says nothing about partitioning up the slave address to
support multiple functions. AFAICT, this is a Qualcomm-created
construct (QPNP) for the 8x41 PMICs. It's difficult to tell at this
point whether or not other vendors might implement a similarly
partitioned scheme.
I suspect the intent is that implementations make use of logical slave
ID for each function in a multi-function device.
> Can we make the address <usid, [base]> and have the code populate a
> resource based on a reg-names property? That way it would be possible
> to extend it to support gsid in case we want to (would require
> reg-names though).
It is certainly possible, and, as you've seen, is how the current
codeaurora.org tree implements SPMI. But, I'm actually actively trying
to avoid doing so, as it conflates Qualcomm-implementation details and
what is actually in the spec (and not just the address space
partitioning, but also the of_spmi.c[2] parsing must know about
interrupts, which are _also_ completely outside the SPMI spec).
Instead what I hope to do for v3 is either:
A) Make QPNP its own bus type (for which I have a prototyped
implementation). A PMIC driver sits on the SPMI bus and registers
itself as a QPNP controller. QPNP controllers have very
simple 8-bit register read/write operations used by QPNP devices.
B) Effectively the same as A, but gets rid of a special QPNP bus type
and uses mfd/platform devices, similar to other in-tree PMIC drivers
(currently working on prototyping this approach)
> With the hack to Josh's patchset I quickly ported qpnp-revision and
> qpnp-vibrator, and it seems to work quite nicely.
Great! Thanks for testing.
Josh
1: https://www.codeaurora.org/cgit/quic/la/kernel/msm-3.10/tree/drivers/spmi
2: https://www.codeaurora.org/cgit/quic/la/kernel/msm-3.10/tree/drivers/of/of_spmi.c
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WARNING: multiple messages have this Message-ID (diff)
From: Josh Cartwright <joshc@codeaurora.org>
To: Bjorn Andersson <bjorn@kryo.se>
Cc: Stephen Warren <swarren@wwwdotorg.org>,
Grant Likely <grant.likely@linaro.org>,
Rob Herring <rob.herring@calxeda.com>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Pawel Moll <pawel.moll@arm.com>,
Mark Rutland <mark.rutland@arm.com>,
Ian Campbell <ian.campbell@citrix.com>,
Kumar Gala <galak@codeaurora.org>,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-arm-msm@vger.kernel.org,
Sagar Dharia <sdharia@codeaurora.org>,
Gilad Avidov <gavidov@codeaurora.org>,
Michael Bohan <mbohan@codeaurora.org>,
devicetree@vger.kernel.org
Subject: Re: [PATCH RFC v2 3/5] spmi: add generic SPMI controller binding documentation
Date: Mon, 7 Oct 2013 16:17:56 -0500 [thread overview]
Message-ID: <20131007211756.GA1036@joshc.qualcomm.com> (raw)
In-Reply-To: <CAJAp7Oi-bPytsLtsppdanOi_p0Y5vfBriGB-B5by7w5Z7SGU-Q@mail.gmail.com>
Hey Bjorn-
On Sat, Oct 05, 2013 at 11:11:36PM -0700, Bjorn Andersson wrote:
> On Tue, Aug 27, 2013 at 2:55 PM, Stephen Warren <swarren@wwwdotorg.org> wrote:
> > On 08/27/2013 11:01 AM, Josh Cartwright wrote:
> > ...
> > cell 0 - address type (0: master, 1: unique ID, 2: group ID, ...)
>
> I think it would make sense to have the master id as a property of the
> bus,
Except that SPMI supports bus configurations with multiple masters.
Unless by 'bus' you meant 'bus controller' here?
> as you could consider this to indicate different buses and then
> usid, gsid and base being part of the reg.
>
> > cell 1 - address value
>
> I did hack up Josh patchset to read a reg touple of <usid, base>
> instead of just usid. I stored the second value in the spmi_device
> struct for easy access, but maybe it should be done like on
> codeaurora; in a resource?
> I believe this looks nice, but as I haven't read the mipi spec I
> wonder, will there be a case where you don't have an offset/base?
> Should it just be made optional?
The SPMI spec says nothing about partitioning up the slave address to
support multiple functions. AFAICT, this is a Qualcomm-created
construct (QPNP) for the 8x41 PMICs. It's difficult to tell at this
point whether or not other vendors might implement a similarly
partitioned scheme.
I suspect the intent is that implementations make use of logical slave
ID for each function in a multi-function device.
> Can we make the address <usid, [base]> and have the code populate a
> resource based on a reg-names property? That way it would be possible
> to extend it to support gsid in case we want to (would require
> reg-names though).
It is certainly possible, and, as you've seen, is how the current
codeaurora.org tree implements SPMI. But, I'm actually actively trying
to avoid doing so, as it conflates Qualcomm-implementation details and
what is actually in the spec (and not just the address space
partitioning, but also the of_spmi.c[2] parsing must know about
interrupts, which are _also_ completely outside the SPMI spec).
Instead what I hope to do for v3 is either:
A) Make QPNP its own bus type (for which I have a prototyped
implementation). A PMIC driver sits on the SPMI bus and registers
itself as a QPNP controller. QPNP controllers have very
simple 8-bit register read/write operations used by QPNP devices.
B) Effectively the same as A, but gets rid of a special QPNP bus type
and uses mfd/platform devices, similar to other in-tree PMIC drivers
(currently working on prototyping this approach)
> With the hack to Josh's patchset I quickly ported qpnp-revision and
> qpnp-vibrator, and it seems to work quite nicely.
Great! Thanks for testing.
Josh
1: https://www.codeaurora.org/cgit/quic/la/kernel/msm-3.10/tree/drivers/spmi
2: https://www.codeaurora.org/cgit/quic/la/kernel/msm-3.10/tree/drivers/of/of_spmi.c
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by The Linux Foundation
WARNING: multiple messages have this Message-ID (diff)
From: joshc@codeaurora.org (Josh Cartwright)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH RFC v2 3/5] spmi: add generic SPMI controller binding documentation
Date: Mon, 7 Oct 2013 16:17:56 -0500 [thread overview]
Message-ID: <20131007211756.GA1036@joshc.qualcomm.com> (raw)
In-Reply-To: <CAJAp7Oi-bPytsLtsppdanOi_p0Y5vfBriGB-B5by7w5Z7SGU-Q@mail.gmail.com>
Hey Bjorn-
On Sat, Oct 05, 2013 at 11:11:36PM -0700, Bjorn Andersson wrote:
> On Tue, Aug 27, 2013 at 2:55 PM, Stephen Warren <swarren@wwwdotorg.org> wrote:
> > On 08/27/2013 11:01 AM, Josh Cartwright wrote:
> > ...
> > cell 0 - address type (0: master, 1: unique ID, 2: group ID, ...)
>
> I think it would make sense to have the master id as a property of the
> bus,
Except that SPMI supports bus configurations with multiple masters.
Unless by 'bus' you meant 'bus controller' here?
> as you could consider this to indicate different buses and then
> usid, gsid and base being part of the reg.
>
> > cell 1 - address value
>
> I did hack up Josh patchset to read a reg touple of <usid, base>
> instead of just usid. I stored the second value in the spmi_device
> struct for easy access, but maybe it should be done like on
> codeaurora; in a resource?
> I believe this looks nice, but as I haven't read the mipi spec I
> wonder, will there be a case where you don't have an offset/base?
> Should it just be made optional?
The SPMI spec says nothing about partitioning up the slave address to
support multiple functions. AFAICT, this is a Qualcomm-created
construct (QPNP) for the 8x41 PMICs. It's difficult to tell at this
point whether or not other vendors might implement a similarly
partitioned scheme.
I suspect the intent is that implementations make use of logical slave
ID for each function in a multi-function device.
> Can we make the address <usid, [base]> and have the code populate a
> resource based on a reg-names property? That way it would be possible
> to extend it to support gsid in case we want to (would require
> reg-names though).
It is certainly possible, and, as you've seen, is how the current
codeaurora.org tree implements SPMI. But, I'm actually actively trying
to avoid doing so, as it conflates Qualcomm-implementation details and
what is actually in the spec (and not just the address space
partitioning, but also the of_spmi.c[2] parsing must know about
interrupts, which are _also_ completely outside the SPMI spec).
Instead what I hope to do for v3 is either:
A) Make QPNP its own bus type (for which I have a prototyped
implementation). A PMIC driver sits on the SPMI bus and registers
itself as a QPNP controller. QPNP controllers have very
simple 8-bit register read/write operations used by QPNP devices.
B) Effectively the same as A, but gets rid of a special QPNP bus type
and uses mfd/platform devices, similar to other in-tree PMIC drivers
(currently working on prototyping this approach)
> With the hack to Josh's patchset I quickly ported qpnp-revision and
> qpnp-vibrator, and it seems to work quite nicely.
Great! Thanks for testing.
Josh
1: https://www.codeaurora.org/cgit/quic/la/kernel/msm-3.10/tree/drivers/spmi
2: https://www.codeaurora.org/cgit/quic/la/kernel/msm-3.10/tree/drivers/of/of_spmi.c
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by The Linux Foundation
next prev parent reply other threads:[~2013-10-07 21:17 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-08-22 20:18 [PATCH RFC v2 0/3] Add support for the System Power Management Interface (SPMI) Josh Cartwright
2013-08-22 20:18 ` Josh Cartwright
2012-12-10 19:41 ` [PATCH RFC v2 1/5] of: Add empty for_each_available_child_of_node() macro definition Josh Cartwright
2013-08-22 22:57 ` Josh Cartwright
2013-08-09 20:37 ` [PATCH RFC v2 4/5] spmi: Add MSM PMIC Arbiter SPMI controller Josh Cartwright
2013-08-09 20:37 ` Josh Cartwright
2013-08-09 20:37 ` [PATCH RFC v2 5/5] spmi: document the PMIC arbiter SPMI bindings Josh Cartwright
2013-08-09 20:37 ` Josh Cartwright
2013-08-23 21:55 ` Stephen Warren
2013-08-23 21:55 ` Stephen Warren
2013-08-09 20:37 ` [PATCH RFC v2 2/5] spmi: Linux driver framework for SPMI Josh Cartwright
2013-08-09 20:37 ` Josh Cartwright
2013-08-22 23:10 ` Greg Kroah-Hartman
2013-08-22 23:10 ` Greg Kroah-Hartman
2013-08-23 16:06 ` Josh Cartwright
2013-08-23 16:06 ` Josh Cartwright
2013-09-09 15:52 ` Mark Brown
2013-09-09 15:52 ` Mark Brown
2013-09-09 16:56 ` Josh Cartwright
2013-09-09 16:56 ` Josh Cartwright
2013-08-22 19:59 ` [PATCH RFC v2 3/5] spmi: add generic SPMI controller binding documentation Josh Cartwright
2013-08-22 19:59 ` Josh Cartwright
2013-08-23 21:58 ` Stephen Warren
2013-08-23 21:58 ` Stephen Warren
2013-08-27 17:01 ` Josh Cartwright
2013-08-27 17:01 ` Josh Cartwright
2013-08-27 21:55 ` Stephen Warren
2013-08-27 21:55 ` Stephen Warren
2013-08-28 18:00 ` Josh Cartwright
2013-08-28 18:00 ` Josh Cartwright
2013-08-28 18:32 ` Stephen Warren
2013-08-28 18:32 ` Stephen Warren
2013-10-06 6:11 ` Bjorn Andersson
2013-10-06 6:11 ` Bjorn Andersson
[not found] ` <CAJAp7Oi-bPytsLtsppdanOi_p0Y5vfBriGB-B5by7w5Z7SGU-Q-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2013-10-07 21:17 ` Josh Cartwright [this message]
2013-10-07 21:17 ` Josh Cartwright
2013-10-07 21:17 ` Josh Cartwright
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