From: Florian Fainelli <f.fainelli@gmail.com> To: linux-arm-kernel@lists.infradead.org Cc: Florian Fainelli <f.fainelli@gmail.com>, Russell King <linux@armlinux.org.uk>, bcm-kernel-feedback-list@broadcom.com (maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE), Jonathan Austin <jonathan.austin@arm.com>, Vladimir Murzin <vladimir.murzin@arm.com>, Thomas Gleixner <tglx@linutronix.de>, Zhaoxiu Zeng <zhaoxiu.zeng@gmail.com>, Mark Rutland <mark.rutland@arm.com>, Nicolas Pitre <nico@linaro.org>, Sebastian Andrzej Siewior <bigeasy@linutronix.de>, Anna-Maria Gleixner <anna-maria@linutronix.de>, linux-kernel@vger.kernel.org (open list), will.deacon@arm.com Subject: [PATCH 5/7] ARM: B15: Add suspend/resume hooks Date: Wed, 18 Jan 2017 12:29:24 -0800 [thread overview] Message-ID: <20170118202927.28740-6-f.fainelli@gmail.com> (raw) In-Reply-To: <20170118202927.28740-1-f.fainelli@gmail.com> The Broadcom Brahma-B15 CPU readahead cache registers will be restored to their Power-on-Reset values after a S3 suspend/resume cycles, so we want to restore what we had enabled before. Another thing we want to take care of is disabling the read-ahead cache prior to suspending to avoid any sort of side effect with the spinlock we need to grab to serialize register accesses. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> --- arch/arm/mm/cache-b15-rac.c | 48 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/arch/arm/mm/cache-b15-rac.c b/arch/arm/mm/cache-b15-rac.c index 81bc6f2abec9..ef5e93e4b5c2 100644 --- a/arch/arm/mm/cache-b15-rac.c +++ b/arch/arm/mm/cache-b15-rac.c @@ -15,6 +15,7 @@ #include <linux/of_address.h> #include <linux/notifier.h> #include <linux/cpu.h> +#include <linux/syscore_ops.h> #include <asm/cacheflush.h> #include <asm/hardware/cache-b15-rac.h> @@ -41,6 +42,10 @@ extern void v7_flush_kern_cache_all(void); RACENPREF_MASK << RACENDATA_SHIFT) #define RAC_ENABLED 0 +/* Special state where we want to bypass the spinlock and call directly + * into the v7 cache maintenance operations during suspend/resume + */ +#define RAC_SUSPENDED 1 static void __iomem *b15_rac_base; static DEFINE_SPINLOCK(rac_lock); @@ -96,6 +101,12 @@ void b15_flush_##name(void) \ unsigned int do_flush; \ u32 val = 0; \ \ + if (test_bit(RAC_SUSPENDED, &b15_rac_flags)) { \ + v7_flush_##name(); \ + bar; \ + return; \ + } \ + \ spin_lock(&rac_lock); \ do_flush = test_bit(RAC_ENABLED, &b15_rac_flags); \ if (do_flush) \ @@ -208,6 +219,39 @@ static int b15_rac_dead_cpu(unsigned int cpu) } #endif /* CONFIG_HOTPLUG_CPU */ +#ifdef CONFIG_PM_SLEEP +static int b15_rac_suspend(void) +{ + /* Suspend the read-ahead cache oeprations, forcing our cache + * implementation to fallback to the regular ARMv7 calls. + * + * We are guaranteed to be running on the boot CPU at this point and + * with every other CPU quiesced, so setting RAC_SUSPENDED is not racy + * here. + */ + rac_config0_reg = b15_rac_disable_and_flush(); + set_bit(RAC_SUSPENDED, &b15_rac_flags); + + return 0; +} + +static void b15_rac_resume(void) +{ + /* Coming out of a S3 suspend/resume cycle, the read-ahead cache + * register RAC_CONFIG0_REG will be restored to its default value, make + * sure we re-enable it and set the enable flag, we are also guaranteed + * to run on the boot CPU, so not racy again. + */ + __b15_rac_enable(rac_config0_reg); + clear_bit(RAC_SUSPENDED, &b15_rac_flags); +} + +static struct syscore_ops b15_rac_syscore_ops = { + .suspend = b15_rac_suspend, + .resume = b15_rac_resume, +}; +#endif + static int __init b15_rac_init(void) { struct device_node *dn; @@ -242,6 +286,10 @@ static int __init b15_rac_init(void) goto out_cpu_dead; #endif +#ifdef CONFIG_PM_SLEEP + register_syscore_ops(&b15_rac_syscore_ops); +#endif + spin_lock(&rac_lock); reg = __raw_readl(b15_rac_base + RAC_CONFIG0_REG); for_each_possible_cpu(cpu) -- 2.9.3
WARNING: multiple messages have this Message-ID (diff)
From: f.fainelli@gmail.com (Florian Fainelli) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 5/7] ARM: B15: Add suspend/resume hooks Date: Wed, 18 Jan 2017 12:29:24 -0800 [thread overview] Message-ID: <20170118202927.28740-6-f.fainelli@gmail.com> (raw) In-Reply-To: <20170118202927.28740-1-f.fainelli@gmail.com> The Broadcom Brahma-B15 CPU readahead cache registers will be restored to their Power-on-Reset values after a S3 suspend/resume cycles, so we want to restore what we had enabled before. Another thing we want to take care of is disabling the read-ahead cache prior to suspending to avoid any sort of side effect with the spinlock we need to grab to serialize register accesses. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> --- arch/arm/mm/cache-b15-rac.c | 48 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/arch/arm/mm/cache-b15-rac.c b/arch/arm/mm/cache-b15-rac.c index 81bc6f2abec9..ef5e93e4b5c2 100644 --- a/arch/arm/mm/cache-b15-rac.c +++ b/arch/arm/mm/cache-b15-rac.c @@ -15,6 +15,7 @@ #include <linux/of_address.h> #include <linux/notifier.h> #include <linux/cpu.h> +#include <linux/syscore_ops.h> #include <asm/cacheflush.h> #include <asm/hardware/cache-b15-rac.h> @@ -41,6 +42,10 @@ extern void v7_flush_kern_cache_all(void); RACENPREF_MASK << RACENDATA_SHIFT) #define RAC_ENABLED 0 +/* Special state where we want to bypass the spinlock and call directly + * into the v7 cache maintenance operations during suspend/resume + */ +#define RAC_SUSPENDED 1 static void __iomem *b15_rac_base; static DEFINE_SPINLOCK(rac_lock); @@ -96,6 +101,12 @@ void b15_flush_##name(void) \ unsigned int do_flush; \ u32 val = 0; \ \ + if (test_bit(RAC_SUSPENDED, &b15_rac_flags)) { \ + v7_flush_##name(); \ + bar; \ + return; \ + } \ + \ spin_lock(&rac_lock); \ do_flush = test_bit(RAC_ENABLED, &b15_rac_flags); \ if (do_flush) \ @@ -208,6 +219,39 @@ static int b15_rac_dead_cpu(unsigned int cpu) } #endif /* CONFIG_HOTPLUG_CPU */ +#ifdef CONFIG_PM_SLEEP +static int b15_rac_suspend(void) +{ + /* Suspend the read-ahead cache oeprations, forcing our cache + * implementation to fallback to the regular ARMv7 calls. + * + * We are guaranteed to be running on the boot CPU@this point and + * with every other CPU quiesced, so setting RAC_SUSPENDED is not racy + * here. + */ + rac_config0_reg = b15_rac_disable_and_flush(); + set_bit(RAC_SUSPENDED, &b15_rac_flags); + + return 0; +} + +static void b15_rac_resume(void) +{ + /* Coming out of a S3 suspend/resume cycle, the read-ahead cache + * register RAC_CONFIG0_REG will be restored to its default value, make + * sure we re-enable it and set the enable flag, we are also guaranteed + * to run on the boot CPU, so not racy again. + */ + __b15_rac_enable(rac_config0_reg); + clear_bit(RAC_SUSPENDED, &b15_rac_flags); +} + +static struct syscore_ops b15_rac_syscore_ops = { + .suspend = b15_rac_suspend, + .resume = b15_rac_resume, +}; +#endif + static int __init b15_rac_init(void) { struct device_node *dn; @@ -242,6 +286,10 @@ static int __init b15_rac_init(void) goto out_cpu_dead; #endif +#ifdef CONFIG_PM_SLEEP + register_syscore_ops(&b15_rac_syscore_ops); +#endif + spin_lock(&rac_lock); reg = __raw_readl(b15_rac_base + RAC_CONFIG0_REG); for_each_possible_cpu(cpu) -- 2.9.3
next prev parent reply other threads:[~2017-01-18 20:31 UTC|newest] Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top 2017-01-18 20:29 [PATCH 0/7] ARM: Broadcom Brahma-B15 readahead cache support Florian Fainelli 2017-01-18 20:29 ` Florian Fainelli 2017-01-18 20:29 ` [PATCH 1/7] ARM: v7: allow setting different cache functions Florian Fainelli 2017-01-18 20:29 ` Florian Fainelli 2017-01-18 20:29 ` [PATCH 2/7] ARM: Add Broadcom Brahma-B15 readahead cache support Florian Fainelli 2017-01-18 20:29 ` Florian Fainelli 2017-01-18 22:56 ` Russell King - ARM Linux 2017-01-18 22:56 ` Russell King - ARM Linux 2017-01-19 0:18 ` Florian Fainelli 2017-01-19 0:18 ` Florian Fainelli 2017-01-18 20:29 ` [PATCH 3/7] ARM: Hook B15 readahead cache functions based on processor Florian Fainelli 2017-01-18 20:29 ` Florian Fainelli 2017-01-18 20:29 ` [PATCH 4/7] ARM: B15: Add CPU hotplug awareness Florian Fainelli 2017-01-18 20:29 ` Florian Fainelli 2017-01-18 20:29 ` Florian Fainelli [this message] 2017-01-18 20:29 ` [PATCH 5/7] ARM: B15: Add suspend/resume hooks Florian Fainelli 2017-01-18 20:29 ` [PATCH 6/7] ARM: B15: Register reboot notifier for KEXEC Florian Fainelli 2017-01-18 20:29 ` Florian Fainelli 2017-01-18 20:29 ` [PATCH 7/7] MAINTAINERS: Update brcmstb entries to cover B15 code Florian Fainelli 2017-01-18 20:29 ` Florian Fainelli 2017-01-18 20:29 ` [PATCH 8/8] ARM: smp: Remove CPU: shutdown notice Florian Fainelli 2017-01-18 20:29 ` Florian Fainelli
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