From: Florian Fainelli <florian.fainelli@broadcom.com>
To: Russell King - ARM Linux <linux@armlinux.org.uk>,
Florian Fainelli <f.fainelli@gmail.com>
Cc: linux-arm-kernel@lists.infradead.org,
Alamy Liu <alamyliu@broadcom.com>,
"maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE"
<bcm-kernel-feedback-list@broadcom.com>,
Jonathan Austin <jonathan.austin@arm.com>,
Vladimir Murzin <vladimir.murzin@arm.com>,
Thomas Gleixner <tglx@linutronix.de>,
Zhaoxiu Zeng <zhaoxiu.zeng@gmail.com>,
Mark Rutland <mark.rutland@arm.com>,
Nicolas Pitre <nico@linaro.org>,
Sebastian Andrzej Siewior <bigeasy@linutronix.de>,
Anna-Maria Gleixner <anna-maria@linutronix.de>,
open list <linux-kernel@vger.kernel.org>,
will.deacon@arm.com
Subject: Re: [PATCH 2/7] ARM: Add Broadcom Brahma-B15 readahead cache support
Date: Wed, 18 Jan 2017 16:18:33 -0800 [thread overview]
Message-ID: <47d36b8c-4786-7077-c623-d2bbc29b8863@broadcom.com> (raw)
In-Reply-To: <20170118225630.GS27312@n2100.armlinux.org.uk>
On 01/18/2017 02:56 PM, Russell King - ARM Linux wrote:
> On Wed, Jan 18, 2017 at 12:29:21PM -0800, Florian Fainelli wrote:
>> The readahead cache only intercepts reads, not writes, as such, some
>> data can remain stale in any of its buffers, such that we need to flush
>> it, which is an operation that needs to happen in a particular order:
>>
>> - disable the readahead cache
>> - flush it
>> - call the appropriate cache-v7.S function
>> - re-enable
>
> I really do hope that the above explanation is wrong, because if that's
> really how it's implemented, it's going to cause coherency problems.
>
> It's got to at least monitor writes, otherwise how do you guarantee
> that the CPU doesn't see stale data? IOW:
Yes, it does monitor writes, the explanation given here was wrong. Thanks!
>
> Consider this at the L2 memory-side interface (iow, downstream of the
> point-of-coherency):
>
> CPU1 CPU2 Read-ahead buffer
> read cache line C
> reads cache line C and C+1
> writes cache line C+1
> read cache line C+1
>
> What ensures that CPU2 sees the written out cache line from CPU1?
--
Florian
WARNING: multiple messages have this Message-ID (diff)
From: florian.fainelli@broadcom.com (Florian Fainelli)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 2/7] ARM: Add Broadcom Brahma-B15 readahead cache support
Date: Wed, 18 Jan 2017 16:18:33 -0800 [thread overview]
Message-ID: <47d36b8c-4786-7077-c623-d2bbc29b8863@broadcom.com> (raw)
In-Reply-To: <20170118225630.GS27312@n2100.armlinux.org.uk>
On 01/18/2017 02:56 PM, Russell King - ARM Linux wrote:
> On Wed, Jan 18, 2017 at 12:29:21PM -0800, Florian Fainelli wrote:
>> The readahead cache only intercepts reads, not writes, as such, some
>> data can remain stale in any of its buffers, such that we need to flush
>> it, which is an operation that needs to happen in a particular order:
>>
>> - disable the readahead cache
>> - flush it
>> - call the appropriate cache-v7.S function
>> - re-enable
>
> I really do hope that the above explanation is wrong, because if that's
> really how it's implemented, it's going to cause coherency problems.
>
> It's got to at least monitor writes, otherwise how do you guarantee
> that the CPU doesn't see stale data? IOW:
Yes, it does monitor writes, the explanation given here was wrong. Thanks!
>
> Consider this at the L2 memory-side interface (iow, downstream of the
> point-of-coherency):
>
> CPU1 CPU2 Read-ahead buffer
> read cache line C
> reads cache line C and C+1
> writes cache line C+1
> read cache line C+1
>
> What ensures that CPU2 sees the written out cache line from CPU1?
--
Florian
next prev parent reply other threads:[~2017-01-19 0:27 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-01-18 20:29 [PATCH 0/7] ARM: Broadcom Brahma-B15 readahead cache support Florian Fainelli
2017-01-18 20:29 ` Florian Fainelli
2017-01-18 20:29 ` [PATCH 1/7] ARM: v7: allow setting different cache functions Florian Fainelli
2017-01-18 20:29 ` Florian Fainelli
2017-01-18 20:29 ` [PATCH 2/7] ARM: Add Broadcom Brahma-B15 readahead cache support Florian Fainelli
2017-01-18 20:29 ` Florian Fainelli
2017-01-18 22:56 ` Russell King - ARM Linux
2017-01-18 22:56 ` Russell King - ARM Linux
2017-01-19 0:18 ` Florian Fainelli [this message]
2017-01-19 0:18 ` Florian Fainelli
2017-01-18 20:29 ` [PATCH 3/7] ARM: Hook B15 readahead cache functions based on processor Florian Fainelli
2017-01-18 20:29 ` Florian Fainelli
2017-01-18 20:29 ` [PATCH 4/7] ARM: B15: Add CPU hotplug awareness Florian Fainelli
2017-01-18 20:29 ` Florian Fainelli
2017-01-18 20:29 ` [PATCH 5/7] ARM: B15: Add suspend/resume hooks Florian Fainelli
2017-01-18 20:29 ` Florian Fainelli
2017-01-18 20:29 ` [PATCH 6/7] ARM: B15: Register reboot notifier for KEXEC Florian Fainelli
2017-01-18 20:29 ` Florian Fainelli
2017-01-18 20:29 ` [PATCH 7/7] MAINTAINERS: Update brcmstb entries to cover B15 code Florian Fainelli
2017-01-18 20:29 ` Florian Fainelli
2017-01-18 20:29 ` [PATCH 8/8] ARM: smp: Remove CPU: shutdown notice Florian Fainelli
2017-01-18 20:29 ` Florian Fainelli
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