From: Kishon Vijay Abraham I <kishon@ti.com>
To: Bjorn Helgaas <bhelgaas@google.com>,
Joao Pinto <Joao.Pinto@synopsys.com>, <linux-pci@vger.kernel.org>,
<linux-doc@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<devicetree@vger.kernel.org>, <linux-omap@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>
Cc: <hch@infradead.org>, <nsekhar@ti.com>, <kishon@ti.com>
Subject: [PATCH v4 10/23] dt-bindings: PCI: Add dt bindings for pci designware EP mode
Date: Mon, 13 Mar 2017 19:52:46 +0530 [thread overview]
Message-ID: <20170313142259.25397-11-kishon@ti.com> (raw)
In-Reply-To: <20170313142259.25397-1-kishon@ti.com>
Add device tree binding documentation for pci designware EP mode.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
.../devicetree/bindings/pci/designware-pcie.txt | 26 +++++++++++++++-------
1 file changed, 18 insertions(+), 8 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt b/Documentation/devicetree/bindings/pci/designware-pcie.txt
index 1392c705ceca..b2480dd38c11 100644
--- a/Documentation/devicetree/bindings/pci/designware-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt
@@ -6,30 +6,40 @@ Required properties:
- reg-names: Must be "config" for the PCIe configuration space.
(The old way of getting the configuration address space from "ranges"
is deprecated and should be avoided.)
+- num-lanes: number of lanes to use
+RC mode:
- #address-cells: set to <3>
- #size-cells: set to <2>
- device_type: set to "pci"
- ranges: ranges for the PCI memory and I/O regions
- #interrupt-cells: set to <1>
-- interrupt-map-mask and interrupt-map: standard PCI properties
- to define the mapping of the PCIe interface to interrupt
+- interrupt-map-mask and interrupt-map: standard PCI
+ properties to define the mapping of the PCIe interface to interrupt
numbers.
-- num-lanes: number of lanes to use
+EP mode:
+- num-ib-windows: number of inbound address translation
+ windows
+- num-ob-windows: number of outbound address translation
+ windows
Optional properties:
-- num-viewport: number of view ports configured in hardware. If a platform
- does not specify it, the driver assumes 2.
- num-lanes: number of lanes to use (this property should be specified unless
the link is brought already up in BIOS)
- reset-gpio: gpio pin number of power good signal
-- bus-range: PCI bus numbers covered (it is recommended for new devicetrees to
- specify this property, to keep backwards compatibility a range of 0x00-0xff
- is assumed if not present)
- clocks: Must contain an entry for each entry in clock-names.
See ../clocks/clock-bindings.txt for details.
- clock-names: Must include the following entries:
- "pcie"
- "pcie_bus"
+RC mode:
+- num-viewport: number of view ports configured in
+ hardware. If a platform does not specify it, the driver assumes 2.
+- bus-range: PCI bus numbers covered (it is recommended
+ for new devicetrees to specify this property, to keep backwards
+ compatibility a range of 0x00-0xff is assumed if not present)
+EP mode:
+- max-functions: maximum number of functions that can be
+ configured
Example configuration:
--
2.11.0
WARNING: multiple messages have this Message-ID (diff)
From: Kishon Vijay Abraham I <kishon@ti.com>
To: Bjorn Helgaas <bhelgaas@google.com>,
Joao Pinto <Joao.Pinto@synopsys.com>,
linux-pci@vger.kernel.org, linux-doc@vger.kernel.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Cc: hch@infradead.org, nsekhar@ti.com, kishon@ti.com
Subject: [PATCH v4 10/23] dt-bindings: PCI: Add dt bindings for pci designware EP mode
Date: Mon, 13 Mar 2017 19:52:46 +0530 [thread overview]
Message-ID: <20170313142259.25397-11-kishon@ti.com> (raw)
In-Reply-To: <20170313142259.25397-1-kishon@ti.com>
Add device tree binding documentation for pci designware EP mode.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
.../devicetree/bindings/pci/designware-pcie.txt | 26 +++++++++++++++-------
1 file changed, 18 insertions(+), 8 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt b/Documentation/devicetree/bindings/pci/designware-pcie.txt
index 1392c705ceca..b2480dd38c11 100644
--- a/Documentation/devicetree/bindings/pci/designware-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt
@@ -6,30 +6,40 @@ Required properties:
- reg-names: Must be "config" for the PCIe configuration space.
(The old way of getting the configuration address space from "ranges"
is deprecated and should be avoided.)
+- num-lanes: number of lanes to use
+RC mode:
- #address-cells: set to <3>
- #size-cells: set to <2>
- device_type: set to "pci"
- ranges: ranges for the PCI memory and I/O regions
- #interrupt-cells: set to <1>
-- interrupt-map-mask and interrupt-map: standard PCI properties
- to define the mapping of the PCIe interface to interrupt
+- interrupt-map-mask and interrupt-map: standard PCI
+ properties to define the mapping of the PCIe interface to interrupt
numbers.
-- num-lanes: number of lanes to use
+EP mode:
+- num-ib-windows: number of inbound address translation
+ windows
+- num-ob-windows: number of outbound address translation
+ windows
Optional properties:
-- num-viewport: number of view ports configured in hardware. If a platform
- does not specify it, the driver assumes 2.
- num-lanes: number of lanes to use (this property should be specified unless
the link is brought already up in BIOS)
- reset-gpio: gpio pin number of power good signal
-- bus-range: PCI bus numbers covered (it is recommended for new devicetrees to
- specify this property, to keep backwards compatibility a range of 0x00-0xff
- is assumed if not present)
- clocks: Must contain an entry for each entry in clock-names.
See ../clocks/clock-bindings.txt for details.
- clock-names: Must include the following entries:
- "pcie"
- "pcie_bus"
+RC mode:
+- num-viewport: number of view ports configured in
+ hardware. If a platform does not specify it, the driver assumes 2.
+- bus-range: PCI bus numbers covered (it is recommended
+ for new devicetrees to specify this property, to keep backwards
+ compatibility a range of 0x00-0xff is assumed if not present)
+EP mode:
+- max-functions: maximum number of functions that can be
+ configured
Example configuration:
--
2.11.0
WARNING: multiple messages have this Message-ID (diff)
From: kishon@ti.com (Kishon Vijay Abraham I)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v4 10/23] dt-bindings: PCI: Add dt bindings for pci designware EP mode
Date: Mon, 13 Mar 2017 19:52:46 +0530 [thread overview]
Message-ID: <20170313142259.25397-11-kishon@ti.com> (raw)
In-Reply-To: <20170313142259.25397-1-kishon@ti.com>
Add device tree binding documentation for pci designware EP mode.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
.../devicetree/bindings/pci/designware-pcie.txt | 26 +++++++++++++++-------
1 file changed, 18 insertions(+), 8 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt b/Documentation/devicetree/bindings/pci/designware-pcie.txt
index 1392c705ceca..b2480dd38c11 100644
--- a/Documentation/devicetree/bindings/pci/designware-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt
@@ -6,30 +6,40 @@ Required properties:
- reg-names: Must be "config" for the PCIe configuration space.
(The old way of getting the configuration address space from "ranges"
is deprecated and should be avoided.)
+- num-lanes: number of lanes to use
+RC mode:
- #address-cells: set to <3>
- #size-cells: set to <2>
- device_type: set to "pci"
- ranges: ranges for the PCI memory and I/O regions
- #interrupt-cells: set to <1>
-- interrupt-map-mask and interrupt-map: standard PCI properties
- to define the mapping of the PCIe interface to interrupt
+- interrupt-map-mask and interrupt-map: standard PCI
+ properties to define the mapping of the PCIe interface to interrupt
numbers.
-- num-lanes: number of lanes to use
+EP mode:
+- num-ib-windows: number of inbound address translation
+ windows
+- num-ob-windows: number of outbound address translation
+ windows
Optional properties:
-- num-viewport: number of view ports configured in hardware. If a platform
- does not specify it, the driver assumes 2.
- num-lanes: number of lanes to use (this property should be specified unless
the link is brought already up in BIOS)
- reset-gpio: gpio pin number of power good signal
-- bus-range: PCI bus numbers covered (it is recommended for new devicetrees to
- specify this property, to keep backwards compatibility a range of 0x00-0xff
- is assumed if not present)
- clocks: Must contain an entry for each entry in clock-names.
See ../clocks/clock-bindings.txt for details.
- clock-names: Must include the following entries:
- "pcie"
- "pcie_bus"
+RC mode:
+- num-viewport: number of view ports configured in
+ hardware. If a platform does not specify it, the driver assumes 2.
+- bus-range: PCI bus numbers covered (it is recommended
+ for new devicetrees to specify this property, to keep backwards
+ compatibility a range of 0x00-0xff is assumed if not present)
+EP mode:
+- max-functions: maximum number of functions that can be
+ configured
Example configuration:
--
2.11.0
next prev parent reply other threads:[~2017-03-13 14:30 UTC|newest]
Thread overview: 95+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-03-13 14:22 [GIT PULL 00/23] PCI: Support for configurable PCI endpoint Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` [PATCH v4 01/23] PCI: endpoint: Add EP core layer to enable EP controller and EP functions Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` [PATCH v4 02/23] Documentation: PCI: Guide to use PCI Endpoint Core Layer Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` [PATCH v4 03/23] PCI: endpoint: Introduce configfs entry for configuring EP functions Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` [PATCH v4 04/23] Documentation: PCI: Guide to use pci endpoint configfs Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` [PATCH v4 05/23] PCI: endpoint: Create configfs entry for EPC device and EPF driver Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` [PATCH v4 06/23] Documentation: PCI: Add specification for the *pci test* function device Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` [PATCH v4 07/23] PCI: endpoint: functions: Add an EP function to test PCI Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` [PATCH v4 08/23] Documentation: PCI: Add binding documentation for pci-test endpoint function Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` [PATCH v4 09/23] PCI: dwc: designware: Add EP mode support Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I [this message]
2017-03-13 14:22 ` [PATCH v4 10/23] dt-bindings: PCI: Add dt bindings for pci designware EP mode Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` [PATCH v4 11/23] PCI: dwc: dra7xx: Facilitate wrapper and msi interrupts to be enabled independently Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` [PATCH v4 12/23] PCI: dwc: dra7xx: Add EP mode support Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` [PATCH v4 13/23] dt-bindings: PCI: dra7xx: Add dt bindings for pci dra7xx EP mode Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` [PATCH v4 14/23] PCI: dwc: dra7xx: Workaround for errata id i870 Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-20 21:48 ` Rob Herring
2017-03-20 21:48 ` Rob Herring
2017-03-22 14:39 ` Kishon Vijay Abraham I
2017-03-22 14:39 ` Kishon Vijay Abraham I
2017-03-22 14:39 ` Kishon Vijay Abraham I
2017-03-22 14:39 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` [PATCH v4 15/23] dt-bindings: PCI: dra7xx: Add dt bindings to enable unaligned access Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-20 21:43 ` Rob Herring
2017-03-20 21:43 ` Rob Herring
2017-03-20 21:43 ` Rob Herring
2017-03-20 21:43 ` Rob Herring
2017-03-22 14:37 ` Kishon Vijay Abraham I
2017-03-22 14:37 ` Kishon Vijay Abraham I
2017-03-22 14:37 ` Kishon Vijay Abraham I
2017-03-22 14:37 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` [PATCH v4 16/23] PCI: Add device IDs for DRA74x and DRA72x Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` [PATCH v4 17/23] misc: Add host side pci driver for pci test function device Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` [PATCH v4 18/23] Documentation: misc-devices: Add Documentation for pci-endpoint-test driver Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` [PATCH v4 19/23] tools: PCI: Add a userspace tool to test PCI endpoint Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` [PATCH v4 20/23] tools: PCI: Add sample test script to invoke pcitest Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` [PATCH v4 21/23] Documentation: PCI: Add userguide for PCI endpoint test function Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` [PATCH v4 22/23] MAINTAINERS: add PCI EP maintainer Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` [PATCH v4 23/23] ARM: DRA7: clockdomain: Change the CLKTRCTRL of CM_PCIE_CLKSTCTRL to SW_WKUP Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
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