From: Kishon Vijay Abraham I <kishon@ti.com>
To: Bjorn Helgaas <bhelgaas@google.com>,
Joao Pinto <Joao.Pinto@synopsys.com>, <linux-pci@vger.kernel.org>,
<linux-doc@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<devicetree@vger.kernel.org>, <linux-omap@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>
Cc: <hch@infradead.org>, <nsekhar@ti.com>, <kishon@ti.com>
Subject: [PATCH v4 13/23] dt-bindings: PCI: dra7xx: Add dt bindings for pci dra7xx EP mode
Date: Mon, 13 Mar 2017 19:52:49 +0530 [thread overview]
Message-ID: <20170313142259.25397-14-kishon@ti.com> (raw)
In-Reply-To: <20170313142259.25397-1-kishon@ti.com>
Add device tree binding documentation for pci dra7xx EP mode.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
Documentation/devicetree/bindings/pci/ti-pci.txt | 37 +++++++++++++++++++-----
1 file changed, 30 insertions(+), 7 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/ti-pci.txt b/Documentation/devicetree/bindings/pci/ti-pci.txt
index 60e25161f351..190828a5f32a 100644
--- a/Documentation/devicetree/bindings/pci/ti-pci.txt
+++ b/Documentation/devicetree/bindings/pci/ti-pci.txt
@@ -1,17 +1,22 @@
TI PCI Controllers
PCIe Designware Controller
- - compatible: Should be "ti,dra7-pcie""
- - reg : Two register ranges as listed in the reg-names property
- - reg-names : The first entry must be "ti-conf" for the TI specific registers
- The second entry must be "rc-dbics" for the designware pcie
- registers
- The third entry must be "config" for the PCIe configuration space
+ - compatible: Should be "ti,dra7-pcie" for RC
+ Should be "ti,dra7-pcie-ep" for EP
- phys : list of PHY specifiers (used by generic PHY framework)
- phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
number of PHYs as specified in *phys* property.
- ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>",
where <X> is the instance number of the pcie from the HW spec.
+ - num-lanes as specified in ../designware-pcie.txt
+
+HOST MODE
+=========
+ - reg : Two register ranges as listed in the reg-names property
+ - reg-names : The first entry must be "ti-conf" for the TI specific registers
+ The second entry must be "rc-dbics" for the designware pcie
+ registers
+ The third entry must be "config" for the PCIe configuration space
- interrupts : Two interrupt entries must be specified. The first one is for
main interrupt line and the second for MSI interrupt line.
- #address-cells,
@@ -19,13 +24,31 @@ PCIe Designware Controller
#interrupt-cells,
device_type,
ranges,
- num-lanes,
interrupt-map-mask,
interrupt-map : as specified in ../designware-pcie.txt
+DEVICE MODE
+===========
+ - reg : Four register ranges as listed in the reg-names property
+ - reg-names : "ti-conf" for the TI specific registers
+ "ep_dbics" for the standard configuration registers as
+ they are locally accessed within the DIF CS space
+ "ep_dbics2" for the standard configuration registers as
+ they are locally accessed within the DIF CS2 space
+ "addr_space" used to map remote RC address space
+ - interrupts : one interrupt entries must be specified for main interrupt.
+ - num-ib-windows : number of inbound address translation windows
+ - num-ob-windows : number of outbound address translation windows
+
Optional Property:
- gpios : Should be added if a gpio line is required to drive PERST# line
+NOTE: Two dt nodes may be added for each PCI controller; one for host
+mode and another for device mode. So in order for PCI to
+work in host mode, EP mode dt node should be disabled and in order to PCI to
+work in EP mode, host mode dt node should be disabled. And host mode and EP
+mode are mutually exclusive.
+
Example:
axi {
compatible = "simple-bus";
--
2.11.0
WARNING: multiple messages have this Message-ID (diff)
From: Kishon Vijay Abraham I <kishon@ti.com>
To: Bjorn Helgaas <bhelgaas@google.com>,
Joao Pinto <Joao.Pinto@synopsys.com>,
linux-pci@vger.kernel.org, linux-doc@vger.kernel.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Cc: hch@infradead.org, nsekhar@ti.com, kishon@ti.com
Subject: [PATCH v4 13/23] dt-bindings: PCI: dra7xx: Add dt bindings for pci dra7xx EP mode
Date: Mon, 13 Mar 2017 19:52:49 +0530 [thread overview]
Message-ID: <20170313142259.25397-14-kishon@ti.com> (raw)
In-Reply-To: <20170313142259.25397-1-kishon@ti.com>
Add device tree binding documentation for pci dra7xx EP mode.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
Documentation/devicetree/bindings/pci/ti-pci.txt | 37 +++++++++++++++++++-----
1 file changed, 30 insertions(+), 7 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/ti-pci.txt b/Documentation/devicetree/bindings/pci/ti-pci.txt
index 60e25161f351..190828a5f32a 100644
--- a/Documentation/devicetree/bindings/pci/ti-pci.txt
+++ b/Documentation/devicetree/bindings/pci/ti-pci.txt
@@ -1,17 +1,22 @@
TI PCI Controllers
PCIe Designware Controller
- - compatible: Should be "ti,dra7-pcie""
- - reg : Two register ranges as listed in the reg-names property
- - reg-names : The first entry must be "ti-conf" for the TI specific registers
- The second entry must be "rc-dbics" for the designware pcie
- registers
- The third entry must be "config" for the PCIe configuration space
+ - compatible: Should be "ti,dra7-pcie" for RC
+ Should be "ti,dra7-pcie-ep" for EP
- phys : list of PHY specifiers (used by generic PHY framework)
- phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
number of PHYs as specified in *phys* property.
- ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>",
where <X> is the instance number of the pcie from the HW spec.
+ - num-lanes as specified in ../designware-pcie.txt
+
+HOST MODE
+=========
+ - reg : Two register ranges as listed in the reg-names property
+ - reg-names : The first entry must be "ti-conf" for the TI specific registers
+ The second entry must be "rc-dbics" for the designware pcie
+ registers
+ The third entry must be "config" for the PCIe configuration space
- interrupts : Two interrupt entries must be specified. The first one is for
main interrupt line and the second for MSI interrupt line.
- #address-cells,
@@ -19,13 +24,31 @@ PCIe Designware Controller
#interrupt-cells,
device_type,
ranges,
- num-lanes,
interrupt-map-mask,
interrupt-map : as specified in ../designware-pcie.txt
+DEVICE MODE
+===========
+ - reg : Four register ranges as listed in the reg-names property
+ - reg-names : "ti-conf" for the TI specific registers
+ "ep_dbics" for the standard configuration registers as
+ they are locally accessed within the DIF CS space
+ "ep_dbics2" for the standard configuration registers as
+ they are locally accessed within the DIF CS2 space
+ "addr_space" used to map remote RC address space
+ - interrupts : one interrupt entries must be specified for main interrupt.
+ - num-ib-windows : number of inbound address translation windows
+ - num-ob-windows : number of outbound address translation windows
+
Optional Property:
- gpios : Should be added if a gpio line is required to drive PERST# line
+NOTE: Two dt nodes may be added for each PCI controller; one for host
+mode and another for device mode. So in order for PCI to
+work in host mode, EP mode dt node should be disabled and in order to PCI to
+work in EP mode, host mode dt node should be disabled. And host mode and EP
+mode are mutually exclusive.
+
Example:
axi {
compatible = "simple-bus";
--
2.11.0
WARNING: multiple messages have this Message-ID (diff)
From: Kishon Vijay Abraham I <kishon@ti.com>
To: Bjorn Helgaas <bhelgaas@google.com>,
Joao Pinto <Joao.Pinto@synopsys.com>, <linux-pci@vger.kernel.org>,
<linux-doc@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<devicetree@vger.kernel.org>, <linux-omap@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>
Cc: hch@infradead.org, nsekhar@ti.com, kishon@ti.com
Subject: [PATCH v4 13/23] dt-bindings: PCI: dra7xx: Add dt bindings for pci dra7xx EP mode
Date: Mon, 13 Mar 2017 19:52:49 +0530 [thread overview]
Message-ID: <20170313142259.25397-14-kishon@ti.com> (raw)
In-Reply-To: <20170313142259.25397-1-kishon@ti.com>
Add device tree binding documentation for pci dra7xx EP mode.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
Documentation/devicetree/bindings/pci/ti-pci.txt | 37 +++++++++++++++++++-----
1 file changed, 30 insertions(+), 7 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/ti-pci.txt b/Documentation/devicetree/bindings/pci/ti-pci.txt
index 60e25161f351..190828a5f32a 100644
--- a/Documentation/devicetree/bindings/pci/ti-pci.txt
+++ b/Documentation/devicetree/bindings/pci/ti-pci.txt
@@ -1,17 +1,22 @@
TI PCI Controllers
PCIe Designware Controller
- - compatible: Should be "ti,dra7-pcie""
- - reg : Two register ranges as listed in the reg-names property
- - reg-names : The first entry must be "ti-conf" for the TI specific registers
- The second entry must be "rc-dbics" for the designware pcie
- registers
- The third entry must be "config" for the PCIe configuration space
+ - compatible: Should be "ti,dra7-pcie" for RC
+ Should be "ti,dra7-pcie-ep" for EP
- phys : list of PHY specifiers (used by generic PHY framework)
- phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
number of PHYs as specified in *phys* property.
- ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>",
where <X> is the instance number of the pcie from the HW spec.
+ - num-lanes as specified in ../designware-pcie.txt
+
+HOST MODE
+=========
+ - reg : Two register ranges as listed in the reg-names property
+ - reg-names : The first entry must be "ti-conf" for the TI specific registers
+ The second entry must be "rc-dbics" for the designware pcie
+ registers
+ The third entry must be "config" for the PCIe configuration space
- interrupts : Two interrupt entries must be specified. The first one is for
main interrupt line and the second for MSI interrupt line.
- #address-cells,
@@ -19,13 +24,31 @@ PCIe Designware Controller
#interrupt-cells,
device_type,
ranges,
- num-lanes,
interrupt-map-mask,
interrupt-map : as specified in ../designware-pcie.txt
+DEVICE MODE
+===========
+ - reg : Four register ranges as listed in the reg-names property
+ - reg-names : "ti-conf" for the TI specific registers
+ "ep_dbics" for the standard configuration registers as
+ they are locally accessed within the DIF CS space
+ "ep_dbics2" for the standard configuration registers as
+ they are locally accessed within the DIF CS2 space
+ "addr_space" used to map remote RC address space
+ - interrupts : one interrupt entries must be specified for main interrupt.
+ - num-ib-windows : number of inbound address translation windows
+ - num-ob-windows : number of outbound address translation windows
+
Optional Property:
- gpios : Should be added if a gpio line is required to drive PERST# line
+NOTE: Two dt nodes may be added for each PCI controller; one for host
+mode and another for device mode. So in order for PCI to
+work in host mode, EP mode dt node should be disabled and in order to PCI to
+work in EP mode, host mode dt node should be disabled. And host mode and EP
+mode are mutually exclusive.
+
Example:
axi {
compatible = "simple-bus";
--
2.11.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
WARNING: multiple messages have this Message-ID (diff)
From: kishon@ti.com (Kishon Vijay Abraham I)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v4 13/23] dt-bindings: PCI: dra7xx: Add dt bindings for pci dra7xx EP mode
Date: Mon, 13 Mar 2017 19:52:49 +0530 [thread overview]
Message-ID: <20170313142259.25397-14-kishon@ti.com> (raw)
In-Reply-To: <20170313142259.25397-1-kishon@ti.com>
Add device tree binding documentation for pci dra7xx EP mode.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
Documentation/devicetree/bindings/pci/ti-pci.txt | 37 +++++++++++++++++++-----
1 file changed, 30 insertions(+), 7 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/ti-pci.txt b/Documentation/devicetree/bindings/pci/ti-pci.txt
index 60e25161f351..190828a5f32a 100644
--- a/Documentation/devicetree/bindings/pci/ti-pci.txt
+++ b/Documentation/devicetree/bindings/pci/ti-pci.txt
@@ -1,17 +1,22 @@
TI PCI Controllers
PCIe Designware Controller
- - compatible: Should be "ti,dra7-pcie""
- - reg : Two register ranges as listed in the reg-names property
- - reg-names : The first entry must be "ti-conf" for the TI specific registers
- The second entry must be "rc-dbics" for the designware pcie
- registers
- The third entry must be "config" for the PCIe configuration space
+ - compatible: Should be "ti,dra7-pcie" for RC
+ Should be "ti,dra7-pcie-ep" for EP
- phys : list of PHY specifiers (used by generic PHY framework)
- phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
number of PHYs as specified in *phys* property.
- ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>",
where <X> is the instance number of the pcie from the HW spec.
+ - num-lanes as specified in ../designware-pcie.txt
+
+HOST MODE
+=========
+ - reg : Two register ranges as listed in the reg-names property
+ - reg-names : The first entry must be "ti-conf" for the TI specific registers
+ The second entry must be "rc-dbics" for the designware pcie
+ registers
+ The third entry must be "config" for the PCIe configuration space
- interrupts : Two interrupt entries must be specified. The first one is for
main interrupt line and the second for MSI interrupt line.
- #address-cells,
@@ -19,13 +24,31 @@ PCIe Designware Controller
#interrupt-cells,
device_type,
ranges,
- num-lanes,
interrupt-map-mask,
interrupt-map : as specified in ../designware-pcie.txt
+DEVICE MODE
+===========
+ - reg : Four register ranges as listed in the reg-names property
+ - reg-names : "ti-conf" for the TI specific registers
+ "ep_dbics" for the standard configuration registers as
+ they are locally accessed within the DIF CS space
+ "ep_dbics2" for the standard configuration registers as
+ they are locally accessed within the DIF CS2 space
+ "addr_space" used to map remote RC address space
+ - interrupts : one interrupt entries must be specified for main interrupt.
+ - num-ib-windows : number of inbound address translation windows
+ - num-ob-windows : number of outbound address translation windows
+
Optional Property:
- gpios : Should be added if a gpio line is required to drive PERST# line
+NOTE: Two dt nodes may be added for each PCI controller; one for host
+mode and another for device mode. So in order for PCI to
+work in host mode, EP mode dt node should be disabled and in order to PCI to
+work in EP mode, host mode dt node should be disabled. And host mode and EP
+mode are mutually exclusive.
+
Example:
axi {
compatible = "simple-bus";
--
2.11.0
next prev parent reply other threads:[~2017-03-13 14:28 UTC|newest]
Thread overview: 95+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-03-13 14:22 [GIT PULL 00/23] PCI: Support for configurable PCI endpoint Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` [PATCH v4 01/23] PCI: endpoint: Add EP core layer to enable EP controller and EP functions Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` [PATCH v4 02/23] Documentation: PCI: Guide to use PCI Endpoint Core Layer Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` [PATCH v4 03/23] PCI: endpoint: Introduce configfs entry for configuring EP functions Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` [PATCH v4 04/23] Documentation: PCI: Guide to use pci endpoint configfs Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` [PATCH v4 05/23] PCI: endpoint: Create configfs entry for EPC device and EPF driver Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` [PATCH v4 06/23] Documentation: PCI: Add specification for the *pci test* function device Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` [PATCH v4 07/23] PCI: endpoint: functions: Add an EP function to test PCI Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` [PATCH v4 08/23] Documentation: PCI: Add binding documentation for pci-test endpoint function Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` [PATCH v4 09/23] PCI: dwc: designware: Add EP mode support Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` [PATCH v4 10/23] dt-bindings: PCI: Add dt bindings for pci designware EP mode Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` [PATCH v4 11/23] PCI: dwc: dra7xx: Facilitate wrapper and msi interrupts to be enabled independently Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` [PATCH v4 12/23] PCI: dwc: dra7xx: Add EP mode support Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I [this message]
2017-03-13 14:22 ` [PATCH v4 13/23] dt-bindings: PCI: dra7xx: Add dt bindings for pci dra7xx EP mode Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` [PATCH v4 14/23] PCI: dwc: dra7xx: Workaround for errata id i870 Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-20 21:48 ` Rob Herring
2017-03-20 21:48 ` Rob Herring
2017-03-22 14:39 ` Kishon Vijay Abraham I
2017-03-22 14:39 ` Kishon Vijay Abraham I
2017-03-22 14:39 ` Kishon Vijay Abraham I
2017-03-22 14:39 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` [PATCH v4 15/23] dt-bindings: PCI: dra7xx: Add dt bindings to enable unaligned access Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-20 21:43 ` Rob Herring
2017-03-20 21:43 ` Rob Herring
2017-03-20 21:43 ` Rob Herring
2017-03-20 21:43 ` Rob Herring
2017-03-22 14:37 ` Kishon Vijay Abraham I
2017-03-22 14:37 ` Kishon Vijay Abraham I
2017-03-22 14:37 ` Kishon Vijay Abraham I
2017-03-22 14:37 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` [PATCH v4 16/23] PCI: Add device IDs for DRA74x and DRA72x Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` [PATCH v4 17/23] misc: Add host side pci driver for pci test function device Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` [PATCH v4 18/23] Documentation: misc-devices: Add Documentation for pci-endpoint-test driver Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` [PATCH v4 19/23] tools: PCI: Add a userspace tool to test PCI endpoint Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` [PATCH v4 20/23] tools: PCI: Add sample test script to invoke pcitest Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` [PATCH v4 21/23] Documentation: PCI: Add userguide for PCI endpoint test function Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` [PATCH v4 22/23] MAINTAINERS: add PCI EP maintainer Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` [PATCH v4 23/23] ARM: DRA7: clockdomain: Change the CLKTRCTRL of CM_PCIE_CLKSTCTRL to SW_WKUP Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
2017-03-13 14:22 ` Kishon Vijay Abraham I
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