From: Icenowy Zheng <icenowy@aosc.io>
To: Maxime Ripard <maxime.ripard@free-electrons.com>,
Rob Herring <robh+dt@kernel.org>, Chen-Yu Tsai <wens@csie.org>,
Jernej Skrabec <jernej.skrabec@siol.net>
Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
linux-sunxi@googlegroups.com, Icenowy Zheng <icenowy@aosc.io>
Subject: [PATCH 01/13] dt-bindings: update the binding for Allwinner H3 DE2 support
Date: Tue, 1 Aug 2017 21:12:52 +0800 [thread overview]
Message-ID: <20170801131304.7741-2-icenowy@aosc.io> (raw)
In-Reply-To: <20170801131304.7741-1-icenowy@aosc.io>
Allwinner H3 features a "Display Engine 2.0".
Add device tree bindings for the following parts:
- H3 TCONs
- H3 Mixers
- H3 Display engine
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
.../bindings/display/sunxi/sun4i-drm.txt | 25 ++++++++++++++++++----
1 file changed, 21 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
index 2ee6ff0ef98e..92512953943e 100644
--- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
+++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
@@ -87,18 +87,17 @@ Required properties:
* allwinner,sun6i-a31-tcon
* allwinner,sun6i-a31s-tcon
* allwinner,sun8i-a33-tcon
+ * allwinner,sun8i-h3-tcon
* allwinner,sun8i-v3s-tcon
- reg: base address and size of memory-mapped region
- interrupts: interrupt associated to this IP
- clocks: phandles to the clocks feeding the TCON. Three are needed:
- 'ahb': the interface clocks
- - 'tcon-ch0': The clock driving the TCON channel 0
- resets: phandles to the reset controllers driving the encoder
- "lcd": the reset line for the TCON channel 0
- clock-names: the clock names mentioned above
- reset-names: the reset names mentioned above
- - clock-output-names: Name of the pixel clock created
- ports: A ports node with endpoint definitions as defined in
Documentation/devicetree/bindings/media/video-interfaces.txt. The
@@ -112,7 +111,23 @@ Required properties:
channel the endpoint is associated to. If that property is not
present, the endpoint number will be used as the channel number.
-On SoCs other than the A33 and V3s, there is one more clock required:
+For the following compatibles:
+ * allwinner,sun5i-a13-tcon
+ * allwinner,sun6i-a31-tcon
+ * allwinner,sun6i-a31s-tcon
+ * allwinner,sun8i-a33-tcon
+ * allwinner,sun8i-v3s-tcon
+there is one more clock and one more property required:
+ - clocks:
+ - 'tcon-ch0': The clock driving the TCON channel 0
+ - clock-output-names: Name of the pixel clock created
+
+For the following compatibles:
+ * allwinner,sun5i-a13-tcon
+ * allwinner,sun6i-a31-tcon
+ * allwinner,sun6i-a31s-tcon
+ * allwinner,sun8i-h3-tcon
+there is one more clock required:
- 'tcon-ch1': The clock driving the TCON channel 1
DRC
@@ -207,6 +222,8 @@ supported.
Required properties:
- compatible: value must be one of:
* allwinner,sun8i-v3s-de2-mixer
+ * allwinner,sun8i-h3-de2-mixer0
+ * allwinner,sun8i-h3-de2-mixer1
- reg: base address and size of the memory-mapped region.
- clocks: phandles to the clocks feeding the mixer
* bus: the mixer interface clock
@@ -218,7 +235,6 @@ Required properties:
Documentation/devicetree/bindings/media/video-interfaces.txt. The
first port should be the input endpoints, the second one the output
-
Display Engine Pipeline
-----------------------
@@ -233,6 +249,7 @@ Required properties:
* allwinner,sun6i-a31-display-engine
* allwinner,sun6i-a31s-display-engine
* allwinner,sun8i-a33-display-engine
+ * allwinner,sun8i-h3-display-engine
* allwinner,sun8i-v3s-display-engine
- allwinner,pipelines: list of phandle to the display engine
--
2.13.0
WARNING: multiple messages have this Message-ID (diff)
From: Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org>
To: Maxime Ripard
<maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>,
Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>,
Jernej Skrabec <jernej.skrabec-gGgVlfcn5nU@public.gmane.org>
Cc: dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org,
Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org>
Subject: [PATCH 01/13] dt-bindings: update the binding for Allwinner H3 DE2 support
Date: Tue, 1 Aug 2017 21:12:52 +0800 [thread overview]
Message-ID: <20170801131304.7741-2-icenowy@aosc.io> (raw)
In-Reply-To: <20170801131304.7741-1-icenowy-h8G6r0blFSE@public.gmane.org>
Allwinner H3 features a "Display Engine 2.0".
Add device tree bindings for the following parts:
- H3 TCONs
- H3 Mixers
- H3 Display engine
Signed-off-by: Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org>
---
.../bindings/display/sunxi/sun4i-drm.txt | 25 ++++++++++++++++++----
1 file changed, 21 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
index 2ee6ff0ef98e..92512953943e 100644
--- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
+++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
@@ -87,18 +87,17 @@ Required properties:
* allwinner,sun6i-a31-tcon
* allwinner,sun6i-a31s-tcon
* allwinner,sun8i-a33-tcon
+ * allwinner,sun8i-h3-tcon
* allwinner,sun8i-v3s-tcon
- reg: base address and size of memory-mapped region
- interrupts: interrupt associated to this IP
- clocks: phandles to the clocks feeding the TCON. Three are needed:
- 'ahb': the interface clocks
- - 'tcon-ch0': The clock driving the TCON channel 0
- resets: phandles to the reset controllers driving the encoder
- "lcd": the reset line for the TCON channel 0
- clock-names: the clock names mentioned above
- reset-names: the reset names mentioned above
- - clock-output-names: Name of the pixel clock created
- ports: A ports node with endpoint definitions as defined in
Documentation/devicetree/bindings/media/video-interfaces.txt. The
@@ -112,7 +111,23 @@ Required properties:
channel the endpoint is associated to. If that property is not
present, the endpoint number will be used as the channel number.
-On SoCs other than the A33 and V3s, there is one more clock required:
+For the following compatibles:
+ * allwinner,sun5i-a13-tcon
+ * allwinner,sun6i-a31-tcon
+ * allwinner,sun6i-a31s-tcon
+ * allwinner,sun8i-a33-tcon
+ * allwinner,sun8i-v3s-tcon
+there is one more clock and one more property required:
+ - clocks:
+ - 'tcon-ch0': The clock driving the TCON channel 0
+ - clock-output-names: Name of the pixel clock created
+
+For the following compatibles:
+ * allwinner,sun5i-a13-tcon
+ * allwinner,sun6i-a31-tcon
+ * allwinner,sun6i-a31s-tcon
+ * allwinner,sun8i-h3-tcon
+there is one more clock required:
- 'tcon-ch1': The clock driving the TCON channel 1
DRC
@@ -207,6 +222,8 @@ supported.
Required properties:
- compatible: value must be one of:
* allwinner,sun8i-v3s-de2-mixer
+ * allwinner,sun8i-h3-de2-mixer0
+ * allwinner,sun8i-h3-de2-mixer1
- reg: base address and size of the memory-mapped region.
- clocks: phandles to the clocks feeding the mixer
* bus: the mixer interface clock
@@ -218,7 +235,6 @@ Required properties:
Documentation/devicetree/bindings/media/video-interfaces.txt. The
first port should be the input endpoints, the second one the output
-
Display Engine Pipeline
-----------------------
@@ -233,6 +249,7 @@ Required properties:
* allwinner,sun6i-a31-display-engine
* allwinner,sun6i-a31s-display-engine
* allwinner,sun8i-a33-display-engine
+ * allwinner,sun8i-h3-display-engine
* allwinner,sun8i-v3s-display-engine
- allwinner,pipelines: list of phandle to the display engine
--
2.13.0
WARNING: multiple messages have this Message-ID (diff)
From: Icenowy Zheng <icenowy@aosc.io>
To: Maxime Ripard <maxime.ripard@free-electrons.com>,
Rob Herring <robh+dt@kernel.org>, Chen-Yu Tsai <wens@csie.org>,
Jernej Skrabec <jernej.skrabec@siol.net>
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
dri-devel@lists.freedesktop.org, linux-sunxi@googlegroups.com,
linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
Icenowy Zheng <icenowy@aosc.io>
Subject: [PATCH 01/13] dt-bindings: update the binding for Allwinner H3 DE2 support
Date: Tue, 1 Aug 2017 21:12:52 +0800 [thread overview]
Message-ID: <20170801131304.7741-2-icenowy@aosc.io> (raw)
In-Reply-To: <20170801131304.7741-1-icenowy@aosc.io>
Allwinner H3 features a "Display Engine 2.0".
Add device tree bindings for the following parts:
- H3 TCONs
- H3 Mixers
- H3 Display engine
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
.../bindings/display/sunxi/sun4i-drm.txt | 25 ++++++++++++++++++----
1 file changed, 21 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
index 2ee6ff0ef98e..92512953943e 100644
--- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
+++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
@@ -87,18 +87,17 @@ Required properties:
* allwinner,sun6i-a31-tcon
* allwinner,sun6i-a31s-tcon
* allwinner,sun8i-a33-tcon
+ * allwinner,sun8i-h3-tcon
* allwinner,sun8i-v3s-tcon
- reg: base address and size of memory-mapped region
- interrupts: interrupt associated to this IP
- clocks: phandles to the clocks feeding the TCON. Three are needed:
- 'ahb': the interface clocks
- - 'tcon-ch0': The clock driving the TCON channel 0
- resets: phandles to the reset controllers driving the encoder
- "lcd": the reset line for the TCON channel 0
- clock-names: the clock names mentioned above
- reset-names: the reset names mentioned above
- - clock-output-names: Name of the pixel clock created
- ports: A ports node with endpoint definitions as defined in
Documentation/devicetree/bindings/media/video-interfaces.txt. The
@@ -112,7 +111,23 @@ Required properties:
channel the endpoint is associated to. If that property is not
present, the endpoint number will be used as the channel number.
-On SoCs other than the A33 and V3s, there is one more clock required:
+For the following compatibles:
+ * allwinner,sun5i-a13-tcon
+ * allwinner,sun6i-a31-tcon
+ * allwinner,sun6i-a31s-tcon
+ * allwinner,sun8i-a33-tcon
+ * allwinner,sun8i-v3s-tcon
+there is one more clock and one more property required:
+ - clocks:
+ - 'tcon-ch0': The clock driving the TCON channel 0
+ - clock-output-names: Name of the pixel clock created
+
+For the following compatibles:
+ * allwinner,sun5i-a13-tcon
+ * allwinner,sun6i-a31-tcon
+ * allwinner,sun6i-a31s-tcon
+ * allwinner,sun8i-h3-tcon
+there is one more clock required:
- 'tcon-ch1': The clock driving the TCON channel 1
DRC
@@ -207,6 +222,8 @@ supported.
Required properties:
- compatible: value must be one of:
* allwinner,sun8i-v3s-de2-mixer
+ * allwinner,sun8i-h3-de2-mixer0
+ * allwinner,sun8i-h3-de2-mixer1
- reg: base address and size of the memory-mapped region.
- clocks: phandles to the clocks feeding the mixer
* bus: the mixer interface clock
@@ -218,7 +235,6 @@ Required properties:
Documentation/devicetree/bindings/media/video-interfaces.txt. The
first port should be the input endpoints, the second one the output
-
Display Engine Pipeline
-----------------------
@@ -233,6 +249,7 @@ Required properties:
* allwinner,sun6i-a31-display-engine
* allwinner,sun6i-a31s-display-engine
* allwinner,sun8i-a33-display-engine
+ * allwinner,sun8i-h3-display-engine
* allwinner,sun8i-v3s-display-engine
- allwinner,pipelines: list of phandle to the display engine
--
2.13.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
WARNING: multiple messages have this Message-ID (diff)
From: icenowy@aosc.io (Icenowy Zheng)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 01/13] dt-bindings: update the binding for Allwinner H3 DE2 support
Date: Tue, 1 Aug 2017 21:12:52 +0800 [thread overview]
Message-ID: <20170801131304.7741-2-icenowy@aosc.io> (raw)
In-Reply-To: <20170801131304.7741-1-icenowy@aosc.io>
Allwinner H3 features a "Display Engine 2.0".
Add device tree bindings for the following parts:
- H3 TCONs
- H3 Mixers
- H3 Display engine
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
.../bindings/display/sunxi/sun4i-drm.txt | 25 ++++++++++++++++++----
1 file changed, 21 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
index 2ee6ff0ef98e..92512953943e 100644
--- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
+++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
@@ -87,18 +87,17 @@ Required properties:
* allwinner,sun6i-a31-tcon
* allwinner,sun6i-a31s-tcon
* allwinner,sun8i-a33-tcon
+ * allwinner,sun8i-h3-tcon
* allwinner,sun8i-v3s-tcon
- reg: base address and size of memory-mapped region
- interrupts: interrupt associated to this IP
- clocks: phandles to the clocks feeding the TCON. Three are needed:
- 'ahb': the interface clocks
- - 'tcon-ch0': The clock driving the TCON channel 0
- resets: phandles to the reset controllers driving the encoder
- "lcd": the reset line for the TCON channel 0
- clock-names: the clock names mentioned above
- reset-names: the reset names mentioned above
- - clock-output-names: Name of the pixel clock created
- ports: A ports node with endpoint definitions as defined in
Documentation/devicetree/bindings/media/video-interfaces.txt. The
@@ -112,7 +111,23 @@ Required properties:
channel the endpoint is associated to. If that property is not
present, the endpoint number will be used as the channel number.
-On SoCs other than the A33 and V3s, there is one more clock required:
+For the following compatibles:
+ * allwinner,sun5i-a13-tcon
+ * allwinner,sun6i-a31-tcon
+ * allwinner,sun6i-a31s-tcon
+ * allwinner,sun8i-a33-tcon
+ * allwinner,sun8i-v3s-tcon
+there is one more clock and one more property required:
+ - clocks:
+ - 'tcon-ch0': The clock driving the TCON channel 0
+ - clock-output-names: Name of the pixel clock created
+
+For the following compatibles:
+ * allwinner,sun5i-a13-tcon
+ * allwinner,sun6i-a31-tcon
+ * allwinner,sun6i-a31s-tcon
+ * allwinner,sun8i-h3-tcon
+there is one more clock required:
- 'tcon-ch1': The clock driving the TCON channel 1
DRC
@@ -207,6 +222,8 @@ supported.
Required properties:
- compatible: value must be one of:
* allwinner,sun8i-v3s-de2-mixer
+ * allwinner,sun8i-h3-de2-mixer0
+ * allwinner,sun8i-h3-de2-mixer1
- reg: base address and size of the memory-mapped region.
- clocks: phandles to the clocks feeding the mixer
* bus: the mixer interface clock
@@ -218,7 +235,6 @@ Required properties:
Documentation/devicetree/bindings/media/video-interfaces.txt. The
first port should be the input endpoints, the second one the output
-
Display Engine Pipeline
-----------------------
@@ -233,6 +249,7 @@ Required properties:
* allwinner,sun6i-a31-display-engine
* allwinner,sun6i-a31s-display-engine
* allwinner,sun8i-a33-display-engine
+ * allwinner,sun8i-h3-display-engine
* allwinner,sun8i-v3s-display-engine
- allwinner,pipelines: list of phandle to the display engine
--
2.13.0
next prev parent reply other threads:[~2017-08-01 13:13 UTC|newest]
Thread overview: 108+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-08-01 13:12 [PATCH 00/13] Allwinner H3 DE2 basical support Icenowy Zheng
2017-08-01 13:12 ` Icenowy Zheng
2017-08-01 13:12 ` Icenowy Zheng
2017-08-01 13:12 ` Icenowy Zheng [this message]
2017-08-01 13:12 ` [PATCH 01/13] dt-bindings: update the binding for Allwinner H3 DE2 support Icenowy Zheng
2017-08-01 13:12 ` Icenowy Zheng
2017-08-01 13:12 ` Icenowy Zheng
2017-08-02 4:53 ` [linux-sunxi] " Jernej Škrabec
2017-08-02 4:53 ` Jernej Škrabec
2017-08-02 4:53 ` Jernej Škrabec
2017-08-02 5:02 ` [linux-sunxi] " icenowy
2017-08-02 5:02 ` icenowy at aosc.io
2017-08-02 5:02 ` icenowy-h8G6r0blFSE
2017-08-02 19:06 ` [linux-sunxi] " Jernej Škrabec
2017-08-02 19:06 ` Jernej Škrabec
2017-08-02 19:06 ` Jernej Škrabec
2017-08-02 22:49 ` [linux-sunxi] " Icenowy Zheng
2017-08-02 22:49 ` Icenowy Zheng
2017-08-02 22:49 ` Icenowy Zheng
2017-08-10 0:21 ` [linux-sunxi] " Rob Herring
2017-08-10 0:21 ` Rob Herring
2017-08-10 0:21 ` Rob Herring
2017-08-16 21:46 ` [linux-sunxi] " Jernej Škrabec
2017-08-16 21:46 ` Jernej Škrabec
2017-08-10 0:18 ` Rob Herring
2017-08-10 0:18 ` Rob Herring
2017-08-10 0:18 ` Rob Herring
2017-08-01 13:12 ` [PATCH 02/13] drm: sun4i: add support for H3 mixers Icenowy Zheng
2017-08-01 13:12 ` Icenowy Zheng
2017-08-01 13:12 ` Icenowy Zheng
2017-08-01 13:12 ` Icenowy Zheng
2017-08-01 13:12 ` [PATCH 03/13] drm: sun4i: add support for H3's TCON Icenowy Zheng
2017-08-01 13:12 ` Icenowy Zheng
2017-08-01 13:12 ` Icenowy Zheng
2017-08-01 13:12 ` Icenowy Zheng
2017-08-04 3:56 ` [linux-sunxi] " Chen-Yu Tsai
2017-08-04 3:56 ` Chen-Yu Tsai
2017-08-04 3:56 ` Chen-Yu Tsai
2017-08-04 3:56 ` Chen-Yu Tsai
2017-08-01 13:12 ` [PATCH 04/13] drm: sun4i: add compatible for H3 display engine Icenowy Zheng
2017-08-01 13:12 ` Icenowy Zheng
2017-08-01 13:12 ` Icenowy Zheng
2017-08-01 13:12 ` Icenowy Zheng
2017-08-01 13:12 ` [PATCH 05/13] clk: sunxi-ng: allow CLK_DE to set CLK_PLL_DE for H3 Icenowy Zheng
2017-08-01 13:12 ` Icenowy Zheng
2017-08-01 13:12 ` Icenowy Zheng
2017-08-01 13:12 ` Icenowy Zheng
2017-08-01 13:12 ` [PATCH 06/13] clk: sunxi-ng: export " Icenowy Zheng
2017-08-01 13:12 ` Icenowy Zheng
2017-08-01 13:12 ` Icenowy Zheng
2017-08-01 13:12 ` Icenowy Zheng
2017-08-01 13:12 ` [PATCH 07/13] ARM: sun8i: h3: add display engine pipeline barebone Icenowy Zheng
2017-08-01 13:12 ` Icenowy Zheng
2017-08-01 13:12 ` Icenowy Zheng
2017-08-01 13:12 ` Icenowy Zheng
2017-08-02 4:47 ` [linux-sunxi] " Jernej Škrabec
2017-08-02 4:47 ` Jernej Škrabec
2017-08-02 5:07 ` icenowy
2017-08-02 5:07 ` icenowy at aosc.io
2017-08-02 5:07 ` icenowy-h8G6r0blFSE
2017-08-21 8:30 ` Maxime Ripard
2017-08-21 8:30 ` Maxime Ripard
2017-08-01 13:12 ` [PATCH 08/13] [NOT FOR REVIEW NOW] drm: bridge: Enable polling hpd event in dw_hdmi Icenowy Zheng
2017-08-01 13:12 ` Icenowy Zheng
2017-08-01 13:12 ` Icenowy Zheng
2017-08-01 13:12 ` Icenowy Zheng
2017-08-01 13:13 ` [PATCH 09/13] [NOT FOR REVIEW NOW] drm: bridge: Add a pre_init function for the dw_hdmi driver Icenowy Zheng
2017-08-01 13:13 ` Icenowy Zheng
2017-08-01 13:13 ` Icenowy Zheng
2017-08-01 13:13 ` Icenowy Zheng
2017-08-01 13:13 ` [PATCH 10/13] [NOT FOR REVIEW NOW] clk: sunxi: Add CLK_SET_RATE_PARENT flag for H3 HDMI clock Icenowy Zheng
2017-08-01 13:13 ` Icenowy Zheng
2017-08-01 13:13 ` Icenowy Zheng
2017-08-01 13:13 ` Icenowy Zheng
2017-08-04 4:15 ` [linux-sunxi] " Chen-Yu Tsai
2017-08-04 4:15 ` Chen-Yu Tsai
2017-08-04 4:15 ` Chen-Yu Tsai
2017-08-04 4:16 ` Icenowy Zheng
2017-08-04 4:16 ` Icenowy Zheng
2017-08-04 4:16 ` Icenowy Zheng
2017-08-04 4:29 ` Chen-Yu Tsai
2017-08-04 4:29 ` Chen-Yu Tsai
2017-08-04 8:59 ` Jernej Škrabec
2017-08-04 8:59 ` Jernej Škrabec
2017-08-04 9:03 ` Icenowy Zheng
2017-08-04 9:03 ` Icenowy Zheng
2017-08-04 9:39 ` Chen-Yu Tsai
2017-08-04 9:39 ` Chen-Yu Tsai
2017-08-04 9:27 ` Chen-Yu Tsai
2017-08-04 9:27 ` Chen-Yu Tsai
2017-08-04 13:49 ` Jernej Škrabec
2017-08-04 13:49 ` Jernej Škrabec
2017-08-04 14:16 ` Chen-Yu Tsai
2017-08-04 14:16 ` Chen-Yu Tsai
2017-08-01 13:13 ` [PATCH 11/13] [NOT FOR REVIEW NOW] drm: sun4i: Add a glue for the DesignWare HDMI controller in H3 Icenowy Zheng
2017-08-01 13:13 ` Icenowy Zheng
2017-08-01 13:13 ` Icenowy Zheng
2017-08-01 13:13 ` Icenowy Zheng
2017-08-01 13:13 ` [PATCH 12/13] [NOT FOR REVIEW NOW] ARM: sun8i: h3: enable DesignWare HDMI controller Icenowy Zheng
2017-08-01 13:13 ` Icenowy Zheng
2017-08-01 13:13 ` Icenowy Zheng
2017-08-01 13:13 ` [PATCH 13/13] [NOT FOR REVIEW NOW] ARM: sun8i: h3: enable HDMI output on Orange Pi PC Icenowy Zheng
2017-08-01 13:13 ` Icenowy Zheng
2017-08-01 13:13 ` Icenowy Zheng
2017-08-01 13:13 ` Icenowy Zheng
2017-08-02 4:46 ` [linux-sunxi] [PATCH 00/13] Allwinner H3 DE2 basical support Chen-Yu Tsai
2017-08-02 4:46 ` Chen-Yu Tsai
2017-08-02 4:46 ` Chen-Yu Tsai
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