From: icenowy@aosc.io
To: "Jernej Škrabec" <jernej.skrabec@siol.net>
Cc: linux-sunxi@googlegroups.com, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
Chen-Yu Tsai <wens@csie.org>, Rob Herring <robh+dt@kernel.org>,
Maxime Ripard <maxime.ripard@free-electrons.com>,
linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: Re: [linux-sunxi] [PATCH 07/13] ARM: sun8i: h3: add display engine pipeline barebone
Date: Wed, 02 Aug 2017 13:07:55 +0800 [thread overview]
Message-ID: <fcbff773f61061bbc0f1d6ffef2a7c35@aosc.io> (raw)
In-Reply-To: <1773537.vAqre0jhCE@jernej-laptop>
在 2017-08-02 12:47，Jernej Škrabec 写道：
> Hi Icenowy,
>
> Dne torek, 01. avgust 2017 ob 15:12:58 CEST je Icenowy Zheng
> napisal(a):
>> As we have already the support for the DE2 on Allwinner H3, add the
>> display engine pipeline device tree nodes to its DTSI file.
>>
>> The H5 pipeline has some differences and will be enabled later.
>>
>> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
>> ---
>> arch/arm/boot/dts/sun8i-h3.dtsi | 170
>> ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 170
>> insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi
>> b/arch/arm/boot/dts/sun8i-h3.dtsi index b36f9f423c39..75ad7b65a7fc
>> 100644
>> --- a/arch/arm/boot/dts/sun8i-h3.dtsi
>> +++ b/arch/arm/boot/dts/sun8i-h3.dtsi
>> @@ -41,6 +41,8 @@
>> */
>>
>> #include "sunxi-h3-h5.dtsi"
>> +#include <dt-bindings/clock/sun8i-de2.h>
>> +#include <dt-bindings/reset/sun8i-de2.h>
>>
>> / {
>> cpus {
>> @@ -72,6 +74,174 @@
>> };
>> };
>>
>> + de: display-engine {
>> + compatible = "allwinner,sun8i-h3-display-engine";
>> + allwinner,pipelines = <&mixer0>,
>> + <&mixer1>;
>> + status = "disabled";
>> + };
>> +
>> + soc {
>> + display_clocks: clock@1000000 {
>> + compatible = "allwinner,sun8i-a83t-de2-clk";
>> + reg = <0x01000000 0x100000>;
>> + clocks = <&ccu CLK_BUS_DE>,
>> + <&ccu CLK_DE>;
>> + clock-names = "bus",
>> + "mod";
>> + resets = <&ccu RST_BUS_DE>;
>> + #clock-cells = <1>;
>> + #reset-cells = <1>;
>> + assigned-clocks = <&ccu CLK_DE>;
>> + assigned-clock-parents = <&ccu CLK_PLL_DE>;
>> + assigned-clock-rates = <432000000>;
>> + };
>
> I believe Maxime ask you to use clk_set_rate() in the past:
> http://lists.infradead.org/pipermail/linux-arm-kernel/2017-June/512909.html
Yes, but I think the frequency is still part of our configuration, not
forced
by the hardware.
If we set it in the driver, why don't we set it to 300MHz?
(In fact for pipelines without TVE we can really use 300MHz for CLK_DE,
and if
we do not want 4K we can even use lower frequency)
>
> Regards,
> Jernej
WARNING: multiple messages have this Message-ID (diff)
From: icenowy-h8G6r0blFSE@public.gmane.org
To: "Jernej Škrabec" <jernej.skrabec-gGgVlfcn5nU@public.gmane.org>
Cc: linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org,
Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>,
Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
Maxime Ripard
<maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>,
linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
Subject: Re: [linux-sunxi] [PATCH 07/13] ARM: sun8i: h3: add display engine pipeline barebone
Date: Wed, 02 Aug 2017 13:07:55 +0800 [thread overview]
Message-ID: <fcbff773f61061bbc0f1d6ffef2a7c35@aosc.io> (raw)
In-Reply-To: <1773537.vAqre0jhCE@jernej-laptop>
在 2017-08-02 12:47，Jernej Škrabec 写道：
> Hi Icenowy,
>
> Dne torek, 01. avgust 2017 ob 15:12:58 CEST je Icenowy Zheng
> napisal(a):
>> As we have already the support for the DE2 on Allwinner H3, add the
>> display engine pipeline device tree nodes to its DTSI file.
>>
>> The H5 pipeline has some differences and will be enabled later.
>>
>> Signed-off-by: Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org>
>> ---
>> arch/arm/boot/dts/sun8i-h3.dtsi | 170
>> ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 170
>> insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi
>> b/arch/arm/boot/dts/sun8i-h3.dtsi index b36f9f423c39..75ad7b65a7fc
>> 100644
>> --- a/arch/arm/boot/dts/sun8i-h3.dtsi
>> +++ b/arch/arm/boot/dts/sun8i-h3.dtsi
>> @@ -41,6 +41,8 @@
>> */
>>
>> #include "sunxi-h3-h5.dtsi"
>> +#include <dt-bindings/clock/sun8i-de2.h>
>> +#include <dt-bindings/reset/sun8i-de2.h>
>>
>> / {
>> cpus {
>> @@ -72,6 +74,174 @@
>> };
>> };
>>
>> + de: display-engine {
>> + compatible = "allwinner,sun8i-h3-display-engine";
>> + allwinner,pipelines = <&mixer0>,
>> + <&mixer1>;
>> + status = "disabled";
>> + };
>> +
>> + soc {
>> + display_clocks: clock@1000000 {
>> + compatible = "allwinner,sun8i-a83t-de2-clk";
>> + reg = <0x01000000 0x100000>;
>> + clocks = <&ccu CLK_BUS_DE>,
>> + <&ccu CLK_DE>;
>> + clock-names = "bus",
>> + "mod";
>> + resets = <&ccu RST_BUS_DE>;
>> + #clock-cells = <1>;
>> + #reset-cells = <1>;
>> + assigned-clocks = <&ccu CLK_DE>;
>> + assigned-clock-parents = <&ccu CLK_PLL_DE>;
>> + assigned-clock-rates = <432000000>;
>> + };
>
> I believe Maxime ask you to use clk_set_rate() in the past:
> http://lists.infradead.org/pipermail/linux-arm-kernel/2017-June/512909.html
Yes, but I think the frequency is still part of our configuration, not
forced
by the hardware.
If we set it in the driver, why don't we set it to 300MHz?
(In fact for pipelines without TVE we can really use 300MHz for CLK_DE,
and if
we do not want 4K we can even use lower frequency)
>
> Regards,
> Jernej
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
WARNING: multiple messages have this Message-ID (diff)
From: icenowy@aosc.io (icenowy at aosc.io)
To: linux-arm-kernel@lists.infradead.org
Subject: [linux-sunxi] [PATCH 07/13] ARM: sun8i: h3: add display engine pipeline barebone
Date: Wed, 02 Aug 2017 13:07:55 +0800 [thread overview]
Message-ID: <fcbff773f61061bbc0f1d6ffef2a7c35@aosc.io> (raw)
In-Reply-To: <1773537.vAqre0jhCE@jernej-laptop>
? 2017-08-02 12:47?Jernej ?krabec ???
> Hi Icenowy,
>
> Dne torek, 01. avgust 2017 ob 15:12:58 CEST je Icenowy Zheng
> napisal(a):
>> As we have already the support for the DE2 on Allwinner H3, add the
>> display engine pipeline device tree nodes to its DTSI file.
>>
>> The H5 pipeline has some differences and will be enabled later.
>>
>> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
>> ---
>> arch/arm/boot/dts/sun8i-h3.dtsi | 170
>> ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 170
>> insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi
>> b/arch/arm/boot/dts/sun8i-h3.dtsi index b36f9f423c39..75ad7b65a7fc
>> 100644
>> --- a/arch/arm/boot/dts/sun8i-h3.dtsi
>> +++ b/arch/arm/boot/dts/sun8i-h3.dtsi
>> @@ -41,6 +41,8 @@
>> */
>>
>> #include "sunxi-h3-h5.dtsi"
>> +#include <dt-bindings/clock/sun8i-de2.h>
>> +#include <dt-bindings/reset/sun8i-de2.h>
>>
>> / {
>> cpus {
>> @@ -72,6 +74,174 @@
>> };
>> };
>>
>> + de: display-engine {
>> + compatible = "allwinner,sun8i-h3-display-engine";
>> + allwinner,pipelines = <&mixer0>,
>> + <&mixer1>;
>> + status = "disabled";
>> + };
>> +
>> + soc {
>> + display_clocks: clock at 1000000 {
>> + compatible = "allwinner,sun8i-a83t-de2-clk";
>> + reg = <0x01000000 0x100000>;
>> + clocks = <&ccu CLK_BUS_DE>,
>> + <&ccu CLK_DE>;
>> + clock-names = "bus",
>> + "mod";
>> + resets = <&ccu RST_BUS_DE>;
>> + #clock-cells = <1>;
>> + #reset-cells = <1>;
>> + assigned-clocks = <&ccu CLK_DE>;
>> + assigned-clock-parents = <&ccu CLK_PLL_DE>;
>> + assigned-clock-rates = <432000000>;
>> + };
>
> I believe Maxime ask you to use clk_set_rate() in the past:
> http://lists.infradead.org/pipermail/linux-arm-kernel/2017-June/512909.html
Yes, but I think the frequency is still part of our configuration, not
forced
by the hardware.
If we set it in the driver, why don't we set it to 300MHz?
(In fact for pipelines without TVE we can really use 300MHz for CLK_DE,
and if
we do not want 4K we can even use lower frequency)
>
> Regards,
> Jernej
next prev parent reply other threads:[~2017-08-02 5:07 UTC|newest]
Thread overview: 108+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-08-01 13:12 [PATCH 00/13] Allwinner H3 DE2 basical support Icenowy Zheng
2017-08-01 13:12 ` Icenowy Zheng
2017-08-01 13:12 ` Icenowy Zheng
2017-08-01 13:12 ` [PATCH 01/13] dt-bindings: update the binding for Allwinner H3 DE2 support Icenowy Zheng
2017-08-01 13:12 ` Icenowy Zheng
2017-08-01 13:12 ` Icenowy Zheng
2017-08-01 13:12 ` Icenowy Zheng
2017-08-02 4:53 ` [linux-sunxi] " Jernej Škrabec
2017-08-02 4:53 ` Jernej Škrabec
2017-08-02 4:53 ` Jernej Škrabec
2017-08-02 5:02 ` [linux-sunxi] " icenowy
2017-08-02 5:02 ` icenowy at aosc.io
2017-08-02 5:02 ` icenowy-h8G6r0blFSE
2017-08-02 19:06 ` [linux-sunxi] " Jernej Škrabec
2017-08-02 19:06 ` Jernej Škrabec
2017-08-02 19:06 ` Jernej Škrabec
2017-08-02 22:49 ` [linux-sunxi] " Icenowy Zheng
2017-08-02 22:49 ` Icenowy Zheng
2017-08-02 22:49 ` Icenowy Zheng
2017-08-10 0:21 ` [linux-sunxi] " Rob Herring
2017-08-10 0:21 ` Rob Herring
2017-08-10 0:21 ` Rob Herring
2017-08-16 21:46 ` [linux-sunxi] " Jernej Škrabec
2017-08-16 21:46 ` Jernej Škrabec
2017-08-10 0:18 ` Rob Herring
2017-08-10 0:18 ` Rob Herring
2017-08-10 0:18 ` Rob Herring
2017-08-01 13:12 ` [PATCH 02/13] drm: sun4i: add support for H3 mixers Icenowy Zheng
2017-08-01 13:12 ` Icenowy Zheng
2017-08-01 13:12 ` Icenowy Zheng
2017-08-01 13:12 ` Icenowy Zheng
2017-08-01 13:12 ` [PATCH 03/13] drm: sun4i: add support for H3's TCON Icenowy Zheng
2017-08-01 13:12 ` Icenowy Zheng
2017-08-01 13:12 ` Icenowy Zheng
2017-08-01 13:12 ` Icenowy Zheng
2017-08-04 3:56 ` [linux-sunxi] " Chen-Yu Tsai
2017-08-04 3:56 ` Chen-Yu Tsai
2017-08-04 3:56 ` Chen-Yu Tsai
2017-08-04 3:56 ` Chen-Yu Tsai
2017-08-01 13:12 ` [PATCH 04/13] drm: sun4i: add compatible for H3 display engine Icenowy Zheng
2017-08-01 13:12 ` Icenowy Zheng
2017-08-01 13:12 ` Icenowy Zheng
2017-08-01 13:12 ` Icenowy Zheng
2017-08-01 13:12 ` [PATCH 05/13] clk: sunxi-ng: allow CLK_DE to set CLK_PLL_DE for H3 Icenowy Zheng
2017-08-01 13:12 ` Icenowy Zheng
2017-08-01 13:12 ` Icenowy Zheng
2017-08-01 13:12 ` Icenowy Zheng
2017-08-01 13:12 ` [PATCH 06/13] clk: sunxi-ng: export " Icenowy Zheng
2017-08-01 13:12 ` Icenowy Zheng
2017-08-01 13:12 ` Icenowy Zheng
2017-08-01 13:12 ` Icenowy Zheng
2017-08-01 13:12 ` [PATCH 07/13] ARM: sun8i: h3: add display engine pipeline barebone Icenowy Zheng
2017-08-01 13:12 ` Icenowy Zheng
2017-08-01 13:12 ` Icenowy Zheng
2017-08-01 13:12 ` Icenowy Zheng
2017-08-02 4:47 ` [linux-sunxi] " Jernej Škrabec
2017-08-02 4:47 ` Jernej Škrabec
2017-08-02 5:07 ` icenowy [this message]
2017-08-02 5:07 ` icenowy at aosc.io
2017-08-02 5:07 ` icenowy-h8G6r0blFSE
2017-08-21 8:30 ` Maxime Ripard
2017-08-21 8:30 ` Maxime Ripard
2017-08-01 13:12 ` [PATCH 08/13] [NOT FOR REVIEW NOW] drm: bridge: Enable polling hpd event in dw_hdmi Icenowy Zheng
2017-08-01 13:12 ` Icenowy Zheng
2017-08-01 13:12 ` Icenowy Zheng
2017-08-01 13:12 ` Icenowy Zheng
2017-08-01 13:13 ` [PATCH 09/13] [NOT FOR REVIEW NOW] drm: bridge: Add a pre_init function for the dw_hdmi driver Icenowy Zheng
2017-08-01 13:13 ` Icenowy Zheng
2017-08-01 13:13 ` Icenowy Zheng
2017-08-01 13:13 ` Icenowy Zheng
2017-08-01 13:13 ` [PATCH 10/13] [NOT FOR REVIEW NOW] clk: sunxi: Add CLK_SET_RATE_PARENT flag for H3 HDMI clock Icenowy Zheng
2017-08-01 13:13 ` Icenowy Zheng
2017-08-01 13:13 ` Icenowy Zheng
2017-08-01 13:13 ` Icenowy Zheng
2017-08-04 4:15 ` [linux-sunxi] " Chen-Yu Tsai
2017-08-04 4:15 ` Chen-Yu Tsai
2017-08-04 4:15 ` Chen-Yu Tsai
2017-08-04 4:16 ` Icenowy Zheng
2017-08-04 4:16 ` Icenowy Zheng
2017-08-04 4:16 ` Icenowy Zheng
2017-08-04 4:29 ` Chen-Yu Tsai
2017-08-04 4:29 ` Chen-Yu Tsai
2017-08-04 8:59 ` Jernej Škrabec
2017-08-04 8:59 ` Jernej Škrabec
2017-08-04 9:03 ` Icenowy Zheng
2017-08-04 9:03 ` Icenowy Zheng
2017-08-04 9:39 ` Chen-Yu Tsai
2017-08-04 9:39 ` Chen-Yu Tsai
2017-08-04 9:27 ` Chen-Yu Tsai
2017-08-04 9:27 ` Chen-Yu Tsai
2017-08-04 13:49 ` Jernej Škrabec
2017-08-04 13:49 ` Jernej Škrabec
2017-08-04 14:16 ` Chen-Yu Tsai
2017-08-04 14:16 ` Chen-Yu Tsai
2017-08-01 13:13 ` [PATCH 11/13] [NOT FOR REVIEW NOW] drm: sun4i: Add a glue for the DesignWare HDMI controller in H3 Icenowy Zheng
2017-08-01 13:13 ` Icenowy Zheng
2017-08-01 13:13 ` Icenowy Zheng
2017-08-01 13:13 ` Icenowy Zheng
2017-08-01 13:13 ` [PATCH 12/13] [NOT FOR REVIEW NOW] ARM: sun8i: h3: enable DesignWare HDMI controller Icenowy Zheng
2017-08-01 13:13 ` Icenowy Zheng
2017-08-01 13:13 ` Icenowy Zheng
2017-08-01 13:13 ` [PATCH 13/13] [NOT FOR REVIEW NOW] ARM: sun8i: h3: enable HDMI output on Orange Pi PC Icenowy Zheng
2017-08-01 13:13 ` Icenowy Zheng
2017-08-01 13:13 ` Icenowy Zheng
2017-08-01 13:13 ` Icenowy Zheng
2017-08-02 4:46 ` [linux-sunxi] [PATCH 00/13] Allwinner H3 DE2 basical support Chen-Yu Tsai
2017-08-02 4:46 ` Chen-Yu Tsai
2017-08-02 4:46 ` Chen-Yu Tsai
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=fcbff773f61061bbc0f1d6ffef2a7c35@aosc.io \
--to=icenowy@aosc.io \
--cc=devicetree@vger.kernel.org \
--cc=dri-devel@lists.freedesktop.org \
--cc=jernej.skrabec@siol.net \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-clk@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-sunxi@googlegroups.com \
--cc=maxime.ripard@free-electrons.com \
--cc=robh+dt@kernel.org \
--cc=wens@csie.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.