From: kbuild test robot <lkp@intel.com>
To: Mars Cheng <mars.cheng@mediatek.com>
Cc: kbuild-all@01.org, Matthias Brugger <matthias.bgg@gmail.com>,
Rob Herring <robh+dt@kernel.org>,
Marc Zyngier <marc.zyngier@arm.com>,
Ryder Lee <ryder.lee@mediatek.com>,
Stephen Boyd <sboyd@kernel.org>,
Sean Wang <sean.wang@mediatek.com>,
CC Hwang <cc.hwang@mediatek.com>,
Loda Chou <loda.chou@mediatek.com>,
linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
devicetree@vger.kernel.org, wsd_upstream@mediatek.com,
linux-serial@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org,
Owen Chen <owen.chen@mediatek.com>,
Mars Cheng <mars.cheng@mediatek.com>
Subject: Re: [PATCH v5 06/11] soc: mediatek: add new flow for mtcmos power.
Date: Wed, 18 Jul 2018 04:36:28 +0800 [thread overview]
Message-ID: <201807180456.NRIktFD8%fengguang.wu@intel.com> (raw)
In-Reply-To: <1531817552-17221-7-git-send-email-mars.cheng@mediatek.com>
[-- Attachment #1: Type: text/plain, Size: 7124 bytes --]
Hi Owen,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on robh/for-next]
[also build test ERROR on v4.18-rc5 next-20180717]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Mars-Cheng/Add-basic-SoC-support-for-mt6765/20180717-205540
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: openrisc-allyesconfig (attached as .config)
compiler: or1k-linux-gcc (GCC) 6.0.0 20160327 (experimental)
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=openrisc
All errors (new ones prefixed by >>):
In file included from include/linux/kernel.h:14:0,
from include/linux/clk.h:16,
from drivers/soc/mediatek/mtk-scpsys-ext.c:6:
drivers/soc/mediatek/mtk-scpsys-ext.c: In function 'bus_clk_enable_disable':
>> drivers/soc/mediatek/mtk-scpsys-ext.c:141:12: error: implicit declaration of function '__clk_get_name' [-Werror=implicit-function-declaration]
__clk_get_name(cc->clk));
^
include/linux/printk.h:304:33: note: in definition of macro 'pr_err'
printk(KERN_ERR pr_fmt(fmt), ##__VA_ARGS__)
^~~~~~~~~~~
In file included from include/linux/printk.h:7:0,
from include/linux/kernel.h:14,
from include/linux/clk.h:16,
from drivers/soc/mediatek/mtk-scpsys-ext.c:6:
include/linux/kern_levels.h:5:18: warning: format '%s' expects argument of type 'char *', but argument 3 has type 'int' [-Wformat=]
#define KERN_SOH "\001" /* ASCII Start Of Header */
^
include/linux/kern_levels.h:11:18: note: in expansion of macro 'KERN_SOH'
#define KERN_ERR KERN_SOH "3" /* error conditions */
^~~~~~~~
include/linux/printk.h:304:9: note: in expansion of macro 'KERN_ERR'
printk(KERN_ERR pr_fmt(fmt), ##__VA_ARGS__)
^~~~~~~~
drivers/soc/mediatek/mtk-scpsys-ext.c:139:5: note: in expansion of macro 'pr_err'
pr_err("Failed to %s %s\n",
^~~~~~
cc1: some warnings being treated as errors
vim +/__clk_get_name +141 drivers/soc/mediatek/mtk-scpsys-ext.c
> 6 #include <linux/clk.h>
7 #include <linux/clk-provider.h>
8 #include <linux/slab.h>
9 #include <linux/export.h>
10 #include <linux/mfd/syscon.h>
11 #include <linux/of_device.h>
12 #include <linux/platform_device.h>
13 #include <linux/regmap.h>
14 #include <linux/soc/mediatek/infracfg.h>
15 #include <linux/soc/mediatek/scpsys-ext.h>
16
17
18 #define MAX_CLKS 10
19 #define INFRA "infracfg"
20 #define SMIC "smi_comm"
21
22 static LIST_HEAD(ext_clk_map_list);
23 static LIST_HEAD(ext_attr_map_list);
24
25 static struct regmap *infracfg;
26 static struct regmap *smi_comm;
27
28 enum regmap_type {
29 IFR_TYPE,
30 SMI_TYPE,
31 MAX_REGMAP_TYPE,
32 };
33
34 /**
35 * struct ext_reg_ctrl - set multiple register for bus protect
36 * @regmap: The bus protect regmap, 1: infracfg, 2: other master regmap
37 * such as SMI.
38 * @set_ofs: The set register offset to set corresponding bit to 1.
39 * @clr_ofs: The clr register offset to clear corresponding bit to 0.
40 * @sta_ofs: The status register offset to show bus protect enable/disable.
41 */
42 struct ext_reg_ctrl {
43 enum regmap_type type;
44 u32 set_ofs;
45 u32 clr_ofs;
46 u32 sta_ofs;
47 };
48
49 /**
50 * struct ext_clk_ctrl - enable multiple clks for bus protect
51 * @clk: The clk need to enable before pwr on/bus protect.
52 * @scpd_n: The name present the scpsys domain where the clks belongs to.
53 * @clk_list: The list node linked to ext_clk_map_list.
54 */
55 struct ext_clk_ctrl {
56 struct clk *clk;
57 const char *scpd_n;
58 struct list_head clk_list;
59 };
60
61 struct bus_mask_ops {
62 int (*set)(struct regmap *regmap, u32 set_ofs,
63 u32 sta_ofs, u32 mask);
64 int (*release)(struct regmap *regmap, u32 clr_ofs,
65 u32 sta_ofs, u32 mask);
66 };
67
68 static struct scpsys_ext_attr *__get_attr_parent(const char *parent_n)
69 {
70 struct scpsys_ext_attr *attr;
71
72 if (!parent_n)
73 return ERR_PTR(-EINVAL);
74
75 list_for_each_entry(attr, &ext_attr_map_list, attr_list) {
76 if (attr->scpd_n && !strcmp(parent_n, attr->scpd_n))
77 return attr;
78 }
79
80 return ERR_PTR(-EINVAL);
81 }
82
83 int bus_ctrl_set_release(struct scpsys_ext_attr *attr, bool set)
84 {
85 int i;
86 int ret = 0;
87
88 for (i = 0; i < MAX_STEP_NUM && attr->mask[i].mask; i++) {
89 struct ext_reg_ctrl *rc = attr->mask[i].regs;
90 struct regmap *regmap;
91
92 if (rc->type == IFR_TYPE)
93 regmap = infracfg;
94 else if (rc->type == SMI_TYPE)
95 regmap = smi_comm;
96 else
97 return -EINVAL;
98
99 if (set)
100 ret = attr->mask[i].ops->set(regmap,
101 rc->set_ofs,
102 rc->sta_ofs,
103 attr->mask[i].mask);
104 else
105 ret = attr->mask[i].ops->release(regmap,
106 rc->clr_ofs,
107 rc->sta_ofs,
108 attr->mask[i].mask);
109 }
110
111 return ret;
112 }
113
114 int bus_ctrl_set(struct scpsys_ext_attr *attr)
115 {
116 return bus_ctrl_set_release(attr, CMD_ENABLE);
117 }
118
119 int bus_ctrl_release(struct scpsys_ext_attr *attr)
120 {
121 return bus_ctrl_set_release(attr, CMD_DISABLE);
122 }
123
124 int bus_clk_enable_disable(struct scpsys_ext_attr *attr, bool enable)
125 {
126 int i = 0;
127 int ret = 0;
128 struct ext_clk_ctrl *cc;
129 struct clk *clk[MAX_CLKS];
130
131 list_for_each_entry(cc, &ext_clk_map_list, clk_list) {
132 if (!strcmp(cc->scpd_n, attr->scpd_n)) {
133 if (enable)
134 ret = clk_prepare_enable(cc->clk);
135 else
136 clk_disable_unprepare(cc->clk);
137
138 if (ret) {
139 pr_err("Failed to %s %s\n",
140 enable ? "enable" : "disable",
> 141 __clk_get_name(cc->clk));
142 goto err;
143 } else {
144 clk[i] = cc->clk;
145 i++;
146 }
147 }
148 }
149
150 return ret;
151
152 err:
153 for (--i; i >= 0; i--)
154 if (enable)
155 clk_disable_unprepare(clk[i]);
156 else
157 clk_prepare_enable(clk[i]);
158 return ret;
159 }
160
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 45626 bytes --]
WARNING: multiple messages have this Message-ID (diff)
From: kbuild test robot <lkp@intel.com>
Cc: kbuild-all@01.org, Matthias Brugger <matthias.bgg@gmail.com>,
Rob Herring <robh+dt@kernel.org>,
Marc Zyngier <marc.zyngier@arm.com>,
Ryder Lee <ryder.lee@mediatek.com>,
Stephen Boyd <sboyd@kernel.org>,
Sean Wang <sean.wang@mediatek.com>,
CC Hwang <cc.hwang@mediatek.com>,
Loda Chou <loda.chou@mediatek.com>,
linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
devicetree@vger.kernel.org, wsd_upstream@mediatek.com,
linux-serial@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org,
Owen Chen <owen.chen@mediatek.com>,
Mars Cheng <mars.cheng@mediatek.com>
Subject: Re: [PATCH v5 06/11] soc: mediatek: add new flow for mtcmos power.
Date: Wed, 18 Jul 2018 04:36:28 +0800 [thread overview]
Message-ID: <201807180456.NRIktFD8%fengguang.wu@intel.com> (raw)
In-Reply-To: <1531817552-17221-7-git-send-email-mars.cheng@mediatek.com>
[-- Attachment #1: Type: text/plain, Size: 7124 bytes --]
Hi Owen,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on robh/for-next]
[also build test ERROR on v4.18-rc5 next-20180717]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Mars-Cheng/Add-basic-SoC-support-for-mt6765/20180717-205540
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: openrisc-allyesconfig (attached as .config)
compiler: or1k-linux-gcc (GCC) 6.0.0 20160327 (experimental)
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=openrisc
All errors (new ones prefixed by >>):
In file included from include/linux/kernel.h:14:0,
from include/linux/clk.h:16,
from drivers/soc/mediatek/mtk-scpsys-ext.c:6:
drivers/soc/mediatek/mtk-scpsys-ext.c: In function 'bus_clk_enable_disable':
>> drivers/soc/mediatek/mtk-scpsys-ext.c:141:12: error: implicit declaration of function '__clk_get_name' [-Werror=implicit-function-declaration]
__clk_get_name(cc->clk));
^
include/linux/printk.h:304:33: note: in definition of macro 'pr_err'
printk(KERN_ERR pr_fmt(fmt), ##__VA_ARGS__)
^~~~~~~~~~~
In file included from include/linux/printk.h:7:0,
from include/linux/kernel.h:14,
from include/linux/clk.h:16,
from drivers/soc/mediatek/mtk-scpsys-ext.c:6:
include/linux/kern_levels.h:5:18: warning: format '%s' expects argument of type 'char *', but argument 3 has type 'int' [-Wformat=]
#define KERN_SOH "\001" /* ASCII Start Of Header */
^
include/linux/kern_levels.h:11:18: note: in expansion of macro 'KERN_SOH'
#define KERN_ERR KERN_SOH "3" /* error conditions */
^~~~~~~~
include/linux/printk.h:304:9: note: in expansion of macro 'KERN_ERR'
printk(KERN_ERR pr_fmt(fmt), ##__VA_ARGS__)
^~~~~~~~
drivers/soc/mediatek/mtk-scpsys-ext.c:139:5: note: in expansion of macro 'pr_err'
pr_err("Failed to %s %s\n",
^~~~~~
cc1: some warnings being treated as errors
vim +/__clk_get_name +141 drivers/soc/mediatek/mtk-scpsys-ext.c
> 6 #include <linux/clk.h>
7 #include <linux/clk-provider.h>
8 #include <linux/slab.h>
9 #include <linux/export.h>
10 #include <linux/mfd/syscon.h>
11 #include <linux/of_device.h>
12 #include <linux/platform_device.h>
13 #include <linux/regmap.h>
14 #include <linux/soc/mediatek/infracfg.h>
15 #include <linux/soc/mediatek/scpsys-ext.h>
16
17
18 #define MAX_CLKS 10
19 #define INFRA "infracfg"
20 #define SMIC "smi_comm"
21
22 static LIST_HEAD(ext_clk_map_list);
23 static LIST_HEAD(ext_attr_map_list);
24
25 static struct regmap *infracfg;
26 static struct regmap *smi_comm;
27
28 enum regmap_type {
29 IFR_TYPE,
30 SMI_TYPE,
31 MAX_REGMAP_TYPE,
32 };
33
34 /**
35 * struct ext_reg_ctrl - set multiple register for bus protect
36 * @regmap: The bus protect regmap, 1: infracfg, 2: other master regmap
37 * such as SMI.
38 * @set_ofs: The set register offset to set corresponding bit to 1.
39 * @clr_ofs: The clr register offset to clear corresponding bit to 0.
40 * @sta_ofs: The status register offset to show bus protect enable/disable.
41 */
42 struct ext_reg_ctrl {
43 enum regmap_type type;
44 u32 set_ofs;
45 u32 clr_ofs;
46 u32 sta_ofs;
47 };
48
49 /**
50 * struct ext_clk_ctrl - enable multiple clks for bus protect
51 * @clk: The clk need to enable before pwr on/bus protect.
52 * @scpd_n: The name present the scpsys domain where the clks belongs to.
53 * @clk_list: The list node linked to ext_clk_map_list.
54 */
55 struct ext_clk_ctrl {
56 struct clk *clk;
57 const char *scpd_n;
58 struct list_head clk_list;
59 };
60
61 struct bus_mask_ops {
62 int (*set)(struct regmap *regmap, u32 set_ofs,
63 u32 sta_ofs, u32 mask);
64 int (*release)(struct regmap *regmap, u32 clr_ofs,
65 u32 sta_ofs, u32 mask);
66 };
67
68 static struct scpsys_ext_attr *__get_attr_parent(const char *parent_n)
69 {
70 struct scpsys_ext_attr *attr;
71
72 if (!parent_n)
73 return ERR_PTR(-EINVAL);
74
75 list_for_each_entry(attr, &ext_attr_map_list, attr_list) {
76 if (attr->scpd_n && !strcmp(parent_n, attr->scpd_n))
77 return attr;
78 }
79
80 return ERR_PTR(-EINVAL);
81 }
82
83 int bus_ctrl_set_release(struct scpsys_ext_attr *attr, bool set)
84 {
85 int i;
86 int ret = 0;
87
88 for (i = 0; i < MAX_STEP_NUM && attr->mask[i].mask; i++) {
89 struct ext_reg_ctrl *rc = attr->mask[i].regs;
90 struct regmap *regmap;
91
92 if (rc->type == IFR_TYPE)
93 regmap = infracfg;
94 else if (rc->type == SMI_TYPE)
95 regmap = smi_comm;
96 else
97 return -EINVAL;
98
99 if (set)
100 ret = attr->mask[i].ops->set(regmap,
101 rc->set_ofs,
102 rc->sta_ofs,
103 attr->mask[i].mask);
104 else
105 ret = attr->mask[i].ops->release(regmap,
106 rc->clr_ofs,
107 rc->sta_ofs,
108 attr->mask[i].mask);
109 }
110
111 return ret;
112 }
113
114 int bus_ctrl_set(struct scpsys_ext_attr *attr)
115 {
116 return bus_ctrl_set_release(attr, CMD_ENABLE);
117 }
118
119 int bus_ctrl_release(struct scpsys_ext_attr *attr)
120 {
121 return bus_ctrl_set_release(attr, CMD_DISABLE);
122 }
123
124 int bus_clk_enable_disable(struct scpsys_ext_attr *attr, bool enable)
125 {
126 int i = 0;
127 int ret = 0;
128 struct ext_clk_ctrl *cc;
129 struct clk *clk[MAX_CLKS];
130
131 list_for_each_entry(cc, &ext_clk_map_list, clk_list) {
132 if (!strcmp(cc->scpd_n, attr->scpd_n)) {
133 if (enable)
134 ret = clk_prepare_enable(cc->clk);
135 else
136 clk_disable_unprepare(cc->clk);
137
138 if (ret) {
139 pr_err("Failed to %s %s\n",
140 enable ? "enable" : "disable",
> 141 __clk_get_name(cc->clk));
142 goto err;
143 } else {
144 clk[i] = cc->clk;
145 i++;
146 }
147 }
148 }
149
150 return ret;
151
152 err:
153 for (--i; i >= 0; i--)
154 if (enable)
155 clk_disable_unprepare(clk[i]);
156 else
157 clk_prepare_enable(clk[i]);
158 return ret;
159 }
160
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 45626 bytes --]
WARNING: multiple messages have this Message-ID (diff)
From: lkp@intel.com (kbuild test robot)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v5 06/11] soc: mediatek: add new flow for mtcmos power.
Date: Wed, 18 Jul 2018 04:36:28 +0800 [thread overview]
Message-ID: <201807180456.NRIktFD8%fengguang.wu@intel.com> (raw)
In-Reply-To: <1531817552-17221-7-git-send-email-mars.cheng@mediatek.com>
Hi Owen,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on robh/for-next]
[also build test ERROR on v4.18-rc5 next-20180717]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Mars-Cheng/Add-basic-SoC-support-for-mt6765/20180717-205540
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: openrisc-allyesconfig (attached as .config)
compiler: or1k-linux-gcc (GCC) 6.0.0 20160327 (experimental)
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=openrisc
All errors (new ones prefixed by >>):
In file included from include/linux/kernel.h:14:0,
from include/linux/clk.h:16,
from drivers/soc/mediatek/mtk-scpsys-ext.c:6:
drivers/soc/mediatek/mtk-scpsys-ext.c: In function 'bus_clk_enable_disable':
>> drivers/soc/mediatek/mtk-scpsys-ext.c:141:12: error: implicit declaration of function '__clk_get_name' [-Werror=implicit-function-declaration]
__clk_get_name(cc->clk));
^
include/linux/printk.h:304:33: note: in definition of macro 'pr_err'
printk(KERN_ERR pr_fmt(fmt), ##__VA_ARGS__)
^~~~~~~~~~~
In file included from include/linux/printk.h:7:0,
from include/linux/kernel.h:14,
from include/linux/clk.h:16,
from drivers/soc/mediatek/mtk-scpsys-ext.c:6:
include/linux/kern_levels.h:5:18: warning: format '%s' expects argument of type 'char *', but argument 3 has type 'int' [-Wformat=]
#define KERN_SOH "\001" /* ASCII Start Of Header */
^
include/linux/kern_levels.h:11:18: note: in expansion of macro 'KERN_SOH'
#define KERN_ERR KERN_SOH "3" /* error conditions */
^~~~~~~~
include/linux/printk.h:304:9: note: in expansion of macro 'KERN_ERR'
printk(KERN_ERR pr_fmt(fmt), ##__VA_ARGS__)
^~~~~~~~
drivers/soc/mediatek/mtk-scpsys-ext.c:139:5: note: in expansion of macro 'pr_err'
pr_err("Failed to %s %s\n",
^~~~~~
cc1: some warnings being treated as errors
vim +/__clk_get_name +141 drivers/soc/mediatek/mtk-scpsys-ext.c
> 6 #include <linux/clk.h>
7 #include <linux/clk-provider.h>
8 #include <linux/slab.h>
9 #include <linux/export.h>
10 #include <linux/mfd/syscon.h>
11 #include <linux/of_device.h>
12 #include <linux/platform_device.h>
13 #include <linux/regmap.h>
14 #include <linux/soc/mediatek/infracfg.h>
15 #include <linux/soc/mediatek/scpsys-ext.h>
16
17
18 #define MAX_CLKS 10
19 #define INFRA "infracfg"
20 #define SMIC "smi_comm"
21
22 static LIST_HEAD(ext_clk_map_list);
23 static LIST_HEAD(ext_attr_map_list);
24
25 static struct regmap *infracfg;
26 static struct regmap *smi_comm;
27
28 enum regmap_type {
29 IFR_TYPE,
30 SMI_TYPE,
31 MAX_REGMAP_TYPE,
32 };
33
34 /**
35 * struct ext_reg_ctrl - set multiple register for bus protect
36 * @regmap: The bus protect regmap, 1: infracfg, 2: other master regmap
37 * such as SMI.
38 * @set_ofs: The set register offset to set corresponding bit to 1.
39 * @clr_ofs: The clr register offset to clear corresponding bit to 0.
40 * @sta_ofs: The status register offset to show bus protect enable/disable.
41 */
42 struct ext_reg_ctrl {
43 enum regmap_type type;
44 u32 set_ofs;
45 u32 clr_ofs;
46 u32 sta_ofs;
47 };
48
49 /**
50 * struct ext_clk_ctrl - enable multiple clks for bus protect
51 * @clk: The clk need to enable before pwr on/bus protect.
52 * @scpd_n: The name present the scpsys domain where the clks belongs to.
53 * @clk_list: The list node linked to ext_clk_map_list.
54 */
55 struct ext_clk_ctrl {
56 struct clk *clk;
57 const char *scpd_n;
58 struct list_head clk_list;
59 };
60
61 struct bus_mask_ops {
62 int (*set)(struct regmap *regmap, u32 set_ofs,
63 u32 sta_ofs, u32 mask);
64 int (*release)(struct regmap *regmap, u32 clr_ofs,
65 u32 sta_ofs, u32 mask);
66 };
67
68 static struct scpsys_ext_attr *__get_attr_parent(const char *parent_n)
69 {
70 struct scpsys_ext_attr *attr;
71
72 if (!parent_n)
73 return ERR_PTR(-EINVAL);
74
75 list_for_each_entry(attr, &ext_attr_map_list, attr_list) {
76 if (attr->scpd_n && !strcmp(parent_n, attr->scpd_n))
77 return attr;
78 }
79
80 return ERR_PTR(-EINVAL);
81 }
82
83 int bus_ctrl_set_release(struct scpsys_ext_attr *attr, bool set)
84 {
85 int i;
86 int ret = 0;
87
88 for (i = 0; i < MAX_STEP_NUM && attr->mask[i].mask; i++) {
89 struct ext_reg_ctrl *rc = attr->mask[i].regs;
90 struct regmap *regmap;
91
92 if (rc->type == IFR_TYPE)
93 regmap = infracfg;
94 else if (rc->type == SMI_TYPE)
95 regmap = smi_comm;
96 else
97 return -EINVAL;
98
99 if (set)
100 ret = attr->mask[i].ops->set(regmap,
101 rc->set_ofs,
102 rc->sta_ofs,
103 attr->mask[i].mask);
104 else
105 ret = attr->mask[i].ops->release(regmap,
106 rc->clr_ofs,
107 rc->sta_ofs,
108 attr->mask[i].mask);
109 }
110
111 return ret;
112 }
113
114 int bus_ctrl_set(struct scpsys_ext_attr *attr)
115 {
116 return bus_ctrl_set_release(attr, CMD_ENABLE);
117 }
118
119 int bus_ctrl_release(struct scpsys_ext_attr *attr)
120 {
121 return bus_ctrl_set_release(attr, CMD_DISABLE);
122 }
123
124 int bus_clk_enable_disable(struct scpsys_ext_attr *attr, bool enable)
125 {
126 int i = 0;
127 int ret = 0;
128 struct ext_clk_ctrl *cc;
129 struct clk *clk[MAX_CLKS];
130
131 list_for_each_entry(cc, &ext_clk_map_list, clk_list) {
132 if (!strcmp(cc->scpd_n, attr->scpd_n)) {
133 if (enable)
134 ret = clk_prepare_enable(cc->clk);
135 else
136 clk_disable_unprepare(cc->clk);
137
138 if (ret) {
139 pr_err("Failed to %s %s\n",
140 enable ? "enable" : "disable",
> 141 __clk_get_name(cc->clk));
142 goto err;
143 } else {
144 clk[i] = cc->clk;
145 i++;
146 }
147 }
148 }
149
150 return ret;
151
152 err:
153 for (--i; i >= 0; i--)
154 if (enable)
155 clk_disable_unprepare(clk[i]);
156 else
157 clk_prepare_enable(clk[i]);
158 return ret;
159 }
160
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
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next prev parent reply other threads:[~2018-07-17 20:37 UTC|newest]
Thread overview: 96+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-07-17 8:52 [PATCH v5 0/11] Add basic SoC support for mt6765 Mars Cheng
2018-07-17 8:52 ` Mars Cheng
2018-07-17 8:52 ` Mars Cheng
2018-07-17 8:52 ` [PATCH v5 01/11] dt-bindings: clock: mediatek: document clk bindings for Mediatek MT6765 SoC Mars Cheng
2018-07-17 8:52 ` Mars Cheng
2018-07-17 8:52 ` Mars Cheng
2018-07-17 8:52 ` Mars Cheng
2018-07-20 17:43 ` Rob Herring
2018-07-20 17:43 ` Rob Herring
2018-08-13 9:12 ` Owen Chen
2018-08-13 9:12 ` Owen Chen
2018-08-13 9:12 ` Owen Chen
2018-07-17 8:52 ` [PATCH v5 02/11] dt-bindings: mediatek: Add smi dts binding " Mars Cheng
2018-07-17 8:52 ` Mars Cheng
2018-07-17 8:52 ` Mars Cheng
2018-07-20 17:44 ` Rob Herring
2018-07-20 17:44 ` Rob Herring
2018-07-17 8:52 ` [PATCH v5 03/11] dt-bindings: mediatek: add MT6765 power dt-bindings Mars Cheng
2018-07-17 8:52 ` Mars Cheng
2018-07-17 8:52 ` Mars Cheng
2018-07-17 8:52 ` Mars Cheng
2018-07-20 17:45 ` Rob Herring
2018-07-20 17:45 ` Rob Herring
2018-07-17 8:52 ` [PATCH v5 04/11] soc: mediatek: add MT6765 scpsys support Mars Cheng
2018-07-17 8:52 ` Mars Cheng
2018-07-17 8:52 ` Mars Cheng
2018-07-17 8:52 ` Mars Cheng
2018-07-17 13:00 ` Sean Wang
2018-07-17 13:00 ` Sean Wang
2018-07-17 13:00 ` Sean Wang
2018-07-18 8:54 ` Mars Cheng
2018-07-18 8:54 ` Mars Cheng
2018-07-18 8:54 ` Mars Cheng
2018-07-20 17:46 ` Rob Herring
2018-07-20 17:46 ` Rob Herring
2018-07-17 8:52 ` [PATCH v5 05/11] clk: mediatek: add mt6765 clock IDs Mars Cheng
2018-07-17 8:52 ` Mars Cheng
2018-07-17 8:52 ` Mars Cheng
2018-07-17 10:24 ` Matthias Brugger
2018-07-17 10:24 ` Matthias Brugger
2018-07-18 4:23 ` Mars Cheng
2018-07-18 4:23 ` Mars Cheng
2018-07-18 4:23 ` Mars Cheng
2018-07-17 8:52 ` [PATCH v5 06/11] soc: mediatek: add new flow for mtcmos power Mars Cheng
2018-07-17 8:52 ` Mars Cheng
2018-07-17 8:52 ` Mars Cheng
2018-07-17 15:49 ` kbuild test robot
2018-07-17 15:49 ` kbuild test robot
2018-07-17 15:49 ` kbuild test robot
2018-07-17 18:19 ` [RFC PATCH] soc: mediatek: bus_ctrl_set_release() can be static kbuild test robot
2018-07-17 18:19 ` kbuild test robot
2018-07-17 18:19 ` kbuild test robot
2018-07-17 18:19 ` [PATCH v5 06/11] soc: mediatek: add new flow for mtcmos power kbuild test robot
2018-07-17 18:19 ` kbuild test robot
2018-07-17 18:19 ` kbuild test robot
2018-07-17 20:36 ` kbuild test robot [this message]
2018-07-17 20:36 ` kbuild test robot
2018-07-17 20:36 ` kbuild test robot
2018-07-18 14:50 ` Matthias Brugger
2018-07-18 14:50 ` Matthias Brugger
2018-07-25 9:42 ` Owen Chen
2018-07-25 9:42 ` Owen Chen
2018-07-25 9:42 ` Owen Chen
2018-07-17 8:52 ` [PATCH v5 07/11] soc: mediatek: add MT6765 subdomain support Mars Cheng
2018-07-17 8:52 ` Mars Cheng
2018-07-17 8:52 ` Mars Cheng
[not found] ` <ce7724590f4e4551be88b76a7355738c@MTKMBS31N1.mediatek.inc>
2018-07-25 9:07 ` Yong Wu
2018-07-25 9:07 ` Yong Wu
2018-07-25 9:16 ` FW: " Yong Wu
2018-07-17 8:52 ` [PATCH v5 08/11] clk: mediatek: fix pll setting Mars Cheng
2018-07-17 8:52 ` Mars Cheng
2018-07-17 8:52 ` Mars Cheng
2018-07-17 8:52 ` [PATCH v5 09/11] clk: mediatek: add new clkmux register API Mars Cheng
2018-07-17 8:52 ` Mars Cheng
2018-07-17 8:52 ` Mars Cheng
2018-07-19 6:57 ` Sean Wang
2018-07-19 6:57 ` Sean Wang
2018-07-19 6:57 ` Sean Wang
2018-08-13 9:09 ` Owen Chen
2018-08-13 9:09 ` Owen Chen
2018-08-13 9:09 ` Owen Chen
2018-07-17 8:52 ` [PATCH v5 10/11] clk: mediatek: Add MT6765 clock support Mars Cheng
2018-07-17 8:52 ` Mars Cheng
2018-07-17 8:52 ` Mars Cheng
2018-07-17 16:09 ` kbuild test robot
2018-07-17 16:09 ` kbuild test robot
2018-07-17 16:09 ` kbuild test robot
2018-07-17 18:52 ` kbuild test robot
2018-07-17 18:52 ` kbuild test robot
2018-07-17 18:52 ` kbuild test robot
2018-07-17 18:52 ` [RFC PATCH] clk: mediatek: cksys_base can be static kbuild test robot
2018-07-17 18:52 ` kbuild test robot
2018-07-17 18:52 ` kbuild test robot
2018-07-17 8:52 ` [PATCH v5 11/11] arm64: dts: mediatek: add mt6765 support Mars Cheng
2018-07-17 8:52 ` Mars Cheng
2018-07-17 8:52 ` Mars Cheng
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