From: Patchwork <patchwork@emeril.freedesktop.org>
To: Chris Wilson <chris@chris-wilson.co.uk>
Cc: intel-gfx@lists.freedesktop.org
Subject: ✗ Fi.CI.SPARSE: warning for series starting with [CI,1/3] drm/i915/execlists: Delay updating ring register state after resume
Date: Fri, 14 Sep 2018 12:51:42 -0000 [thread overview]
Message-ID: <20180914125142.3983.54376@emeril.freedesktop.org> (raw)
In-Reply-To: <20180914123504.2062-1-chris@chris-wilson.co.uk>
== Series Details ==
Series: series starting with [CI,1/3] drm/i915/execlists: Delay updating ring register state after resume
URL : https://patchwork.freedesktop.org/series/49708/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm/i915/execlists: Delay updating ring register state after resume
Okay!
Commit: drm/i915: Check engine->default_state mapping on module load
Okay!
Commit: drm/i915/execlists: Use coherent writes into the context image
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3712:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3718:16: warning: expression using sizeof(void)
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next prev parent reply other threads:[~2018-09-14 12:51 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-09-14 12:35 [CI 1/3] drm/i915/execlists: Delay updating ring register state after resume Chris Wilson
2018-09-14 12:35 ` [CI 2/3] drm/i915: Check engine->default_state mapping on module load Chris Wilson
2018-09-14 12:35 ` [CI 3/3] drm/i915/execlists: Use coherent writes into the context image Chris Wilson
2018-09-14 12:51 ` Patchwork [this message]
2018-09-14 13:10 ` ✓ Fi.CI.BAT: success for series starting with [CI,1/3] drm/i915/execlists: Delay updating ring register state after resume Patchwork
2018-09-14 15:53 ` ✓ Fi.CI.IGT: " Patchwork
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