All of lore.kernel.org
 help / color / mirror / Atom feed
From: Manasi Navare <manasi.d.navare@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [CI v12 21/23] drm/i915/fec: Set FEC_READY in FEC_CONFIGURATION
Date: Tue, 27 Nov 2018 13:41:23 -0800	[thread overview]
Message-ID: <20181127214125.17658-21-manasi.d.navare@intel.com> (raw)
In-Reply-To: <20181127214125.17658-1-manasi.d.navare@intel.com>

From: Anusha Srivatsa <anusha.srivatsa@intel.com>

If the panel supports FEC, the driver has to
set the FEC_READY bit in the dpcd register:
FEC_CONFIGURATION.

This has to happen before link training.

v2: s/intel_dp_set_fec_ready/intel_dp_sink_set_fec_ready
   - change commit message. (Gaurav)

v3: rebased. (r-b Manasi)

v4: Use fec crtc state, before setting FEC_READY
bit. (Anusha)

v5: Move to intel_ddi.c
- Make the function static (Anusha)

v6: Dont pass state as a separate argument (Ville)

v7: (From Manasi)
* Correct the debug print (Ville)

Cc: dri-devel@lists.freedesktop.org
Cc: Gaurav K Singh <gaurav.k.singh@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 6533624226a7..4c74bbe1cf73 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -3102,6 +3102,16 @@ static void icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port)
 	I915_WRITE(MG_DP_MODE(port, 1), ln1);
 }
 
+static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
+					const struct intel_crtc_state *crtc_state)
+{
+	if (!crtc_state->fec_enable)
+		return;
+
+	if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, DP_FEC_READY) <= 0)
+		DRM_DEBUG_KMS("Failed to set FEC_READY in the sink\n");
+}
+
 static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
 				    const struct intel_crtc_state *crtc_state,
 				    const struct drm_connector_state *conn_state)
@@ -3142,6 +3152,7 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
 		intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
 	intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
 					      true);
+	intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
 	intel_dp_start_link_train(intel_dp);
 	if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
 		intel_dp_stop_link_train(intel_dp);
-- 
2.19.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  parent reply	other threads:[~2018-11-27 21:38 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-11-27 21:41 [CI v12 01/23] drm/dsc: Modify DRM helper to return complete DSC color depth capabilities Manasi Navare
2018-11-27 21:41 ` [CI v12 02/23] drm/dsc: Define Display Stream Compression PPS infoframe Manasi Navare
2018-11-27 21:41 ` [CI v12 03/23] drm/dsc: Define VESA Display Stream Compression Capabilities Manasi Navare
2018-11-27 21:41 ` [CI v12 04/23] drm/dsc: Define Rate Control values that do not change over configurations Manasi Navare
2018-11-27 21:41 ` [CI v12 05/23] drm/dsc: Add helpers for DSC picture parameter set infoframes Manasi Navare
2018-11-28  0:04   ` Srivatsa, Anusha
2018-11-27 21:41 ` [CI v12 06/23] drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants Manasi Navare
2018-11-27 21:41 ` [CI v12 07/23] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state Manasi Navare
2018-11-27 21:41 ` [CI v12 08/23] drm/i915/dp: Compute DSC pipe config in atomic check Manasi Navare
2018-11-27 21:41 ` [CI v12 09/23] drm/i915/dp: Do not enable PSR2 if DSC is enabled Manasi Navare
2018-11-27 21:41 ` [CI v12 10/23] drm/i915/dsc: Define & Compute VESA DSC params Manasi Navare
2018-11-27 21:41 ` [CI v12 11/23] drm/i915/dsc: Compute Rate Control parameters for DSC Manasi Navare
2018-11-27 21:41 ` [CI v12 12/23] drm/i915/dp: Enable/Disable DSC in DP Sink Manasi Navare
2018-11-27 21:41 ` [CI v12 13/23] drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI Manasi Navare
2018-11-27 21:41 ` [CI v12 14/23] drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling Manasi Navare
2018-11-27 21:41 ` [CI v12 15/23] drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs Manasi Navare
2018-11-27 21:41 ` [CI v12 16/23] drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes Manasi Navare
2018-11-27 21:41 ` [CI v12 17/23] drm/i915/dp: Configure Display stream splitter registers during DSC enable Manasi Navare
2018-11-27 21:41 ` [CI v12 18/23] drm/i915/dp: Disable DSC in source by disabling DSS CTL bits Manasi Navare
2018-11-27 21:41 ` [CI v12 19/23] drm/i915/dsc: Enable and disable appropriate power wells for VDSC Manasi Navare
2018-11-27 21:41 ` [CI v12 20/23] i915/dp/fec: Add fec_enable to the crtc state Manasi Navare
2018-11-27 21:41 ` Manasi Navare [this message]
2018-11-27 21:41 ` [CI v12 22/23] i915/dp/fec: Configure the Forward Error Correction bits Manasi Navare
2018-11-27 21:41 ` [CI v12 23/23] drm/i915/fec: Disable FEC state Manasi Navare
2018-11-27 22:51 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,v12,01/23] drm/dsc: Modify DRM helper to return complete DSC color depth capabilities Patchwork
2018-11-27 22:59 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-11-27 23:25 ` ✓ Fi.CI.BAT: success " Patchwork
2018-11-28 11:44 ` ✓ Fi.CI.IGT: " Patchwork

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20181127214125.17658-21-manasi.d.navare@intel.com \
    --to=manasi.d.navare@intel.com \
    --cc=intel-gfx@lists.freedesktop.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.