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From: Manasi Navare <manasi.d.navare@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [CI v12 09/23] drm/i915/dp: Do not enable PSR2 if DSC is enabled
Date: Tue, 27 Nov 2018 13:41:11 -0800	[thread overview]
Message-ID: <20181127214125.17658-9-manasi.d.navare@intel.com> (raw)
In-Reply-To: <20181127214125.17658-1-manasi.d.navare@intel.com>

If a eDP panel supports both PSR2 and VDSC, our HW cannot
support both at a time. Give priority to PSR2 if a requested
resolution can be supported without compression else enable
VDSC and keep PSR2 disabled.

v4:
Fix the unrealted stuff removed during rebase (Ville)
v3:
* Rebase
v2:
* Add warning for DSC and PSR2 enabled together (DK)

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_psr.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 572e626eadff..2084784f320d 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -75,6 +75,10 @@ static bool intel_psr2_enabled(struct drm_i915_private *dev_priv,
 	if (i915_modparams.enable_psr == -1)
 		return false;
 
+	/* Cannot enable DSC and PSR2 simultaneously */
+	WARN_ON(crtc_state->dsc_params.compression_enable &&
+		crtc_state->has_psr2);
+
 	switch (dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK) {
 	case I915_PSR_DEBUG_FORCE_PSR1:
 		return false;
@@ -502,6 +506,16 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
 	if (!dev_priv->psr.sink_psr2_support)
 		return false;
 
+	/*
+	 * DSC and PSR2 cannot be enabled simultaneously. If a requested
+	 * resolution requires DSC to be enabled, priority is given to DSC
+	 * over PSR2.
+	 */
+	if (crtc_state->dsc_params.compression_enable) {
+		DRM_DEBUG_KMS("PSR2 cannot be enabled since DSC is enabled\n");
+		return false;
+	}
+
 	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
 		psr_max_h = 4096;
 		psr_max_v = 2304;
-- 
2.19.1

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  parent reply	other threads:[~2018-11-27 21:38 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-11-27 21:41 [CI v12 01/23] drm/dsc: Modify DRM helper to return complete DSC color depth capabilities Manasi Navare
2018-11-27 21:41 ` [CI v12 02/23] drm/dsc: Define Display Stream Compression PPS infoframe Manasi Navare
2018-11-27 21:41 ` [CI v12 03/23] drm/dsc: Define VESA Display Stream Compression Capabilities Manasi Navare
2018-11-27 21:41 ` [CI v12 04/23] drm/dsc: Define Rate Control values that do not change over configurations Manasi Navare
2018-11-27 21:41 ` [CI v12 05/23] drm/dsc: Add helpers for DSC picture parameter set infoframes Manasi Navare
2018-11-28  0:04   ` Srivatsa, Anusha
2018-11-27 21:41 ` [CI v12 06/23] drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants Manasi Navare
2018-11-27 21:41 ` [CI v12 07/23] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state Manasi Navare
2018-11-27 21:41 ` [CI v12 08/23] drm/i915/dp: Compute DSC pipe config in atomic check Manasi Navare
2018-11-27 21:41 ` Manasi Navare [this message]
2018-11-27 21:41 ` [CI v12 10/23] drm/i915/dsc: Define & Compute VESA DSC params Manasi Navare
2018-11-27 21:41 ` [CI v12 11/23] drm/i915/dsc: Compute Rate Control parameters for DSC Manasi Navare
2018-11-27 21:41 ` [CI v12 12/23] drm/i915/dp: Enable/Disable DSC in DP Sink Manasi Navare
2018-11-27 21:41 ` [CI v12 13/23] drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI Manasi Navare
2018-11-27 21:41 ` [CI v12 14/23] drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling Manasi Navare
2018-11-27 21:41 ` [CI v12 15/23] drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs Manasi Navare
2018-11-27 21:41 ` [CI v12 16/23] drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes Manasi Navare
2018-11-27 21:41 ` [CI v12 17/23] drm/i915/dp: Configure Display stream splitter registers during DSC enable Manasi Navare
2018-11-27 21:41 ` [CI v12 18/23] drm/i915/dp: Disable DSC in source by disabling DSS CTL bits Manasi Navare
2018-11-27 21:41 ` [CI v12 19/23] drm/i915/dsc: Enable and disable appropriate power wells for VDSC Manasi Navare
2018-11-27 21:41 ` [CI v12 20/23] i915/dp/fec: Add fec_enable to the crtc state Manasi Navare
2018-11-27 21:41 ` [CI v12 21/23] drm/i915/fec: Set FEC_READY in FEC_CONFIGURATION Manasi Navare
2018-11-27 21:41 ` [CI v12 22/23] i915/dp/fec: Configure the Forward Error Correction bits Manasi Navare
2018-11-27 21:41 ` [CI v12 23/23] drm/i915/fec: Disable FEC state Manasi Navare
2018-11-27 22:51 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,v12,01/23] drm/dsc: Modify DRM helper to return complete DSC color depth capabilities Patchwork
2018-11-27 22:59 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-11-27 23:25 ` ✓ Fi.CI.BAT: success " Patchwork
2018-11-28 11:44 ` ✓ Fi.CI.IGT: " Patchwork

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