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From: Patchwork <patchwork@emeril.freedesktop.org>
To: Manasi Navare <manasi.d.navare@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: ✗ Fi.CI.SPARSE: warning for series starting with [CI,v12,01/23] drm/dsc: Modify DRM helper to return complete DSC color depth capabilities
Date: Tue, 27 Nov 2018 22:59:56 -0000	[thread overview]
Message-ID: <20181127225956.13466.9350@emeril.freedesktop.org> (raw)
In-Reply-To: <20181127214125.17658-1-manasi.d.navare@intel.com>

== Series Details ==

Series: series starting with [CI,v12,01/23] drm/dsc: Modify DRM helper to return complete DSC color depth capabilities
URL   : https://patchwork.freedesktop.org/series/53113/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/dsc: Modify DRM helper to return complete DSC color depth capabilities
Okay!

Commit: drm/dsc: Define Display Stream Compression PPS infoframe
Okay!

Commit: drm/dsc: Define VESA Display Stream Compression Capabilities
Okay!

Commit: drm/dsc: Define Rate Control values that do not change over configurations
Okay!

Commit: drm/dsc: Add helpers for DSC picture parameter set infoframes
-
+drivers/gpu/drm/drm_dsc.c:200:61:    expected restricted __be16 <noident>
+drivers/gpu/drm/drm_dsc.c:200:61:    got int
+drivers/gpu/drm/drm_dsc.c:200:61: warning: incorrect type in assignment (different base types)
+drivers/gpu/drm/drm_dsc.c:207:25:    expected unsigned short [unsigned] [usertype] val
+drivers/gpu/drm/drm_dsc.c:207:25:    got restricted __be16 <noident>
+drivers/gpu/drm/drm_dsc.c:207:25: warning: cast from restricted __be16
+drivers/gpu/drm/drm_dsc.c:207:25: warning: cast from restricted __be16
+drivers/gpu/drm/drm_dsc.c:207:25: warning: cast from restricted __be16
+drivers/gpu/drm/drm_dsc.c:207:25: warning: incorrect type in argument 1 (different base types)

Commit: drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants
Okay!

Commit: drm/i915/dp: Add DSC params and DSC config to intel_crtc_state
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3569:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3570:16: warning: expression using sizeof(void)

Commit: drm/i915/dp: Compute DSC pipe config in atomic check
+drivers/gpu/drm/i915/intel_dp.c:1896:23: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dp.c:1916:25: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dp.c:1916:25: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dp.c:1938:58: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dp.c:1938:58: warning: expression using sizeof(void)

Commit: drm/i915/dp: Do not enable PSR2 if DSC is enabled
Okay!

Commit: drm/i915/dsc: Define & Compute VESA DSC params
+drivers/gpu/drm/i915/intel_vdsc.c:351:17: warning: expression using sizeof(void)
+./include/uapi/linux/perf_event.h:147:56: warning: cast truncates bits from constant value (8000000000000000 becomes 0)

Commit: drm/i915/dsc: Compute Rate Control parameters for DSC
Okay!

Commit: drm/i915/dp: Enable/Disable DSC in DP Sink
Okay!

Commit: drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI
Okay!

Commit: drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3570:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3572:16: warning: expression using sizeof(void)

Commit: drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs
Okay!

Commit: drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes
Okay!

Commit: drm/i915/dp: Configure Display stream splitter registers during DSC enable
Okay!

Commit: drm/i915/dp: Disable DSC in source by disabling DSS CTL bits
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3572:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3573:16: warning: expression using sizeof(void)

Commit: drm/i915/dsc: Enable and disable appropriate power wells for VDSC
Okay!

Commit: i915/dp/fec: Add fec_enable to the crtc state.
Okay!

Commit: drm/i915/fec: Set FEC_READY in FEC_CONFIGURATION
Okay!

Commit: i915/dp/fec: Configure the Forward Error Correction bits.
Okay!

Commit: drm/i915/fec: Disable FEC state.
Okay!

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  parent reply	other threads:[~2018-11-27 22:59 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-11-27 21:41 [CI v12 01/23] drm/dsc: Modify DRM helper to return complete DSC color depth capabilities Manasi Navare
2018-11-27 21:41 ` [CI v12 02/23] drm/dsc: Define Display Stream Compression PPS infoframe Manasi Navare
2018-11-27 21:41 ` [CI v12 03/23] drm/dsc: Define VESA Display Stream Compression Capabilities Manasi Navare
2018-11-27 21:41 ` [CI v12 04/23] drm/dsc: Define Rate Control values that do not change over configurations Manasi Navare
2018-11-27 21:41 ` [CI v12 05/23] drm/dsc: Add helpers for DSC picture parameter set infoframes Manasi Navare
2018-11-28  0:04   ` Srivatsa, Anusha
2018-11-27 21:41 ` [CI v12 06/23] drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants Manasi Navare
2018-11-27 21:41 ` [CI v12 07/23] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state Manasi Navare
2018-11-27 21:41 ` [CI v12 08/23] drm/i915/dp: Compute DSC pipe config in atomic check Manasi Navare
2018-11-27 21:41 ` [CI v12 09/23] drm/i915/dp: Do not enable PSR2 if DSC is enabled Manasi Navare
2018-11-27 21:41 ` [CI v12 10/23] drm/i915/dsc: Define & Compute VESA DSC params Manasi Navare
2018-11-27 21:41 ` [CI v12 11/23] drm/i915/dsc: Compute Rate Control parameters for DSC Manasi Navare
2018-11-27 21:41 ` [CI v12 12/23] drm/i915/dp: Enable/Disable DSC in DP Sink Manasi Navare
2018-11-27 21:41 ` [CI v12 13/23] drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI Manasi Navare
2018-11-27 21:41 ` [CI v12 14/23] drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling Manasi Navare
2018-11-27 21:41 ` [CI v12 15/23] drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs Manasi Navare
2018-11-27 21:41 ` [CI v12 16/23] drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes Manasi Navare
2018-11-27 21:41 ` [CI v12 17/23] drm/i915/dp: Configure Display stream splitter registers during DSC enable Manasi Navare
2018-11-27 21:41 ` [CI v12 18/23] drm/i915/dp: Disable DSC in source by disabling DSS CTL bits Manasi Navare
2018-11-27 21:41 ` [CI v12 19/23] drm/i915/dsc: Enable and disable appropriate power wells for VDSC Manasi Navare
2018-11-27 21:41 ` [CI v12 20/23] i915/dp/fec: Add fec_enable to the crtc state Manasi Navare
2018-11-27 21:41 ` [CI v12 21/23] drm/i915/fec: Set FEC_READY in FEC_CONFIGURATION Manasi Navare
2018-11-27 21:41 ` [CI v12 22/23] i915/dp/fec: Configure the Forward Error Correction bits Manasi Navare
2018-11-27 21:41 ` [CI v12 23/23] drm/i915/fec: Disable FEC state Manasi Navare
2018-11-27 22:51 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,v12,01/23] drm/dsc: Modify DRM helper to return complete DSC color depth capabilities Patchwork
2018-11-27 22:59 ` Patchwork [this message]
2018-11-27 23:25 ` ✓ Fi.CI.BAT: success " Patchwork
2018-11-28 11:44 ` ✓ Fi.CI.IGT: " Patchwork

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