[PATCH 00/15] Enhance CP110 COMPHY support

From: Miquel Raynal <miquel.raynal@bootlin.com>
To: Gregory Clement <gregory.clement@bootlin.com>,
	Jason Cooper <jason@lakedaemon.net>, Andrew Lunn <andrew@lunn.ch>,
	Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>,
	Kishon Vijay Abraham I <kishon@ti.com>
Cc: devicetree@vger.kernel.org,
	Antoine Tenart <antoine.tenart@bootlin.com>,
	Russell King <linux@armlinux.org.uk>,
	Maxime Chevallier <maxime.chevallier@bootlin.com>,
	Nadav Haklai <nadavh@marvell.com>,
	Rob Herring <robh+dt@kernel.org>,
	Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
	Miquel Raynal <miquel.raynal@bootlin.com>,
	linux-arm-kernel@lists.infradead.org
Subject: [PATCH 00/15] Enhance CP110 COMPHY support
Date: Mon,  1 Apr 2019 18:51:16 +0200	[thread overview]
Message-ID: <20190401165131.23370-1-miquel.raynal@bootlin.com> (raw)

Armada CP110 have a COMPHY IP which supports configuring SERDES lanes
in one mode, either:
- SATA
- USB3 host
- PCIe (several width)
- Ethernet (several modes)

As of today, only a few Ethernet modes are supported and the code is
embedded in the Linux driver. A more complete COMPHY driver that can
be used by both Linux and U-Boot is embedded in the firmware and can
be run through SMC calls.

First the current COMPHY driver is updated to use SMC calls but
fallbacks to the already existing functions if the firmware is not
up-to-date. Then, more Ethernet modes are added (through SMC calls
only). SATA, USB3H and PCIe modes are also supported one by one.

There is one subtle difference with the PCIe functions: we must tell
the firmware the number of lanes to configure (x1, x2 or x4). This
parameter depends on the number of entries in the 'phys' property
describing the PCIe PHY. We use the "submode" parameter of the generic
PHY API to carry this value. The Armada-8k PCIe driver has been
updated to follow this idea, see [1].

Finally, as pointed by Rob during a review, there is a phy-supply
property (part of the generic PHY framework) which is supposed to take
over the usb-phy property, while at modifying PHY properties, we do
the translation for COMPHY PHYs.

[1] http://patchwork.ozlabs.org/patch/1072763/

Thanks,
Miquèl

Miquel Raynal (15):
  phy: mvebu-cp110-comphy: Explicitly initialize the lane submode
  phy: mvebu-cp110-comphy: Add SMC call support
  phy: mvebu-cp110-comphy: List already supported Ethernet modes
  phy: mvebu-cp110-comphy: Add RXAUI support
  phy: mvebu-cp110-comphy: Rename the macro handling only Ethernet modes
  phy: mvebu-cp110-comphy: Allow non-Ethernet modes to be configured
  phy: mvebu-cp110-comphy: Add USB3 host/device support
  phy: mvebu-cp110-comphy: Add SATA support
  phy: mvebu-cp110-comphy: Cosmetic change in a helper
  phy: mvebu-cp110-comphy: Add PCIe support
  phy: mvebu-cp110-comphy: Update comment about powering off all lanes
    at boot
  arm64: dts: marvell: Add 7k/8k per-port PHYs in SATA nodes
  arm64: dts: marvell: Add 7k/8k PHYs in USB3 nodes
  arm64: dts: marvell: Add 7k/8k PHYs in PCIe nodes
  arm64: dts: marvell: Convert 7k/8k usb-phy properties to phy-supply

 .../arm64/boot/dts/marvell/armada-7040-db.dts |  37 ++-
 .../marvell/armada-8040-clearfog-gt-8k.dts    |  22 +-
 .../arm64/boot/dts/marvell/armada-8040-db.dts |  43 ++-
 .../boot/dts/marvell/armada-8040-mcbin.dtsi   |  37 ++-
 drivers/phy/marvell/phy-mvebu-cp110-comphy.c  | 293 +++++++++++++++---
 5 files changed, 355 insertions(+), 77 deletions(-)

-- 
2.19.1

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