From: Palmer Dabbelt <palmer@sifive.com> To: Peter Maydell <peter.maydell@linaro.org> Cc: "Wladimir J. van der Laan" <laanwj@gmail.com>, Palmer Dabbelt <palmer@sifive.com>, qemu-devel@nongnu.org, Michael Clark <mjc@sifive.com>, Alistair Francis <alistair.francis@wdc.com>, qemu-riscv@nongnu.org Subject: [Qemu-devel] [PULL 27/32] disas/riscv: Fix `rdinstreth` constraint Date: Wed, 3 Jul 2019 01:40:43 -0700 [thread overview] Message-ID: <20190703084048.6980-28-palmer@sifive.com> (raw) In-Reply-To: <20190703084048.6980-1-palmer@sifive.com> From: "Wladimir J. van der Laan" <laanwj@gmail.com> The constraint for `rdinstreth` was comparing the csr number to 0xc80, which is `cycleh` instead. Fix this. Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com> Signed-off-by: Michael Clark <mjc@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> --- disas/riscv.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/disas/riscv.c b/disas/riscv.c index d37312705516..278d9be9247e 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -614,7 +614,8 @@ static const rvc_constraint rvcc_rdtime[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc01, r static const rvc_constraint rvcc_rdinstret[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc02, rvc_end }; static const rvc_constraint rvcc_rdcycleh[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc80, rvc_end }; static const rvc_constraint rvcc_rdtimeh[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc81, rvc_end }; -static const rvc_constraint rvcc_rdinstreth[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc80, rvc_end }; +static const rvc_constraint rvcc_rdinstreth[] = { rvc_rs1_eq_x0, + rvc_csr_eq_0xc82, rvc_end }; static const rvc_constraint rvcc_frcsr[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x003, rvc_end }; static const rvc_constraint rvcc_frrm[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x002, rvc_end }; static const rvc_constraint rvcc_frflags[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x001, rvc_end }; @@ -1038,7 +1039,7 @@ const rv_opcode_data opcode_data[] = { { "c.srai", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_srai, rv_op_srai, rv_op_srai, rvcd_imm_nz }, { "c.andi", rv_codec_cb_imm, rv_fmt_rd_rs1_imm, NULL, rv_op_andi, - rv_op_andi, rv_op_andi, rvcd_imm_nz }, + rv_op_andi, rv_op_andi }, { "c.sub", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_sub, rv_op_sub, rv_op_sub }, { "c.xor", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_xor, rv_op_xor, rv_op_xor }, { "c.or", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_or, rv_op_or, rv_op_or }, -- 2.21.0
WARNING: multiple messages have this Message-ID (diff)
From: Palmer Dabbelt <palmer@sifive.com> To: Peter Maydell <peter.maydell@linaro.org> Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, "Wladimir J. van der Laan" <laanwj@gmail.com>, Michael Clark <mjc@sifive.com>, Alistair Francis <alistair.francis@wdc.com>, Palmer Dabbelt <palmer@sifive.com> Subject: [Qemu-riscv] [PULL 27/32] disas/riscv: Fix `rdinstreth` constraint Date: Wed, 3 Jul 2019 01:40:43 -0700 [thread overview] Message-ID: <20190703084048.6980-28-palmer@sifive.com> (raw) In-Reply-To: <20190703084048.6980-1-palmer@sifive.com> From: "Wladimir J. van der Laan" <laanwj@gmail.com> The constraint for `rdinstreth` was comparing the csr number to 0xc80, which is `cycleh` instead. Fix this. Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com> Signed-off-by: Michael Clark <mjc@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> --- disas/riscv.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/disas/riscv.c b/disas/riscv.c index d37312705516..278d9be9247e 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -614,7 +614,8 @@ static const rvc_constraint rvcc_rdtime[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc01, r static const rvc_constraint rvcc_rdinstret[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc02, rvc_end }; static const rvc_constraint rvcc_rdcycleh[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc80, rvc_end }; static const rvc_constraint rvcc_rdtimeh[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc81, rvc_end }; -static const rvc_constraint rvcc_rdinstreth[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc80, rvc_end }; +static const rvc_constraint rvcc_rdinstreth[] = { rvc_rs1_eq_x0, + rvc_csr_eq_0xc82, rvc_end }; static const rvc_constraint rvcc_frcsr[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x003, rvc_end }; static const rvc_constraint rvcc_frrm[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x002, rvc_end }; static const rvc_constraint rvcc_frflags[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x001, rvc_end }; @@ -1038,7 +1039,7 @@ const rv_opcode_data opcode_data[] = { { "c.srai", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_srai, rv_op_srai, rv_op_srai, rvcd_imm_nz }, { "c.andi", rv_codec_cb_imm, rv_fmt_rd_rs1_imm, NULL, rv_op_andi, - rv_op_andi, rv_op_andi, rvcd_imm_nz }, + rv_op_andi, rv_op_andi }, { "c.sub", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_sub, rv_op_sub, rv_op_sub }, { "c.xor", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_xor, rv_op_xor, rv_op_xor }, { "c.or", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_or, rv_op_or, rv_op_or }, -- 2.21.0
next prev parent reply other threads:[~2019-07-03 9:14 UTC|newest] Thread overview: 83+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-07-03 8:40 [Qemu-devel] [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 v3 Palmer Dabbelt 2019-07-03 8:40 ` [Qemu-riscv] " Palmer Dabbelt 2019-07-03 8:40 ` [Qemu-devel] [PULL 01/32] target/riscv: Allow setting ISA extensions via CPU props Palmer Dabbelt 2019-07-03 8:40 ` [Qemu-riscv] " Palmer Dabbelt 2019-07-03 8:40 ` [Qemu-devel] [PULL 02/32] sifive_prci: Read and write PRCI registers Palmer Dabbelt 2019-07-03 8:40 ` [Qemu-riscv] " Palmer Dabbelt 2019-07-03 8:40 ` [Qemu-devel] [PULL 03/32] target/riscv: Fix PMP range boundary address bug Palmer Dabbelt 2019-07-03 8:40 ` [Qemu-riscv] " Palmer Dabbelt 2019-07-03 8:40 ` [Qemu-devel] [PULL 04/32] target/riscv: Implement riscv_cpu_unassigned_access Palmer Dabbelt 2019-07-03 8:40 ` [Qemu-riscv] " Palmer Dabbelt 2019-08-01 15:39 ` [Qemu-devel] " Peter Maydell 2019-08-01 15:39 ` [Qemu-riscv] " Peter Maydell 2019-08-13 22:44 ` [Qemu-devel] " Palmer Dabbelt 2019-08-13 22:44 ` [Qemu-riscv] " Palmer Dabbelt 2019-08-15 21:39 ` [Qemu-devel] " Alistair Francis 2019-08-15 21:39 ` [Qemu-riscv] " Alistair Francis 2019-08-15 22:17 ` Palmer Dabbelt 2019-08-15 22:17 ` [Qemu-riscv] " Palmer Dabbelt 2019-08-16 8:57 ` Peter Maydell 2019-08-16 8:57 ` [Qemu-riscv] " Peter Maydell 2019-09-17 13:56 ` Peter Maydell 2019-09-17 13:56 ` [Qemu-riscv] " Peter Maydell 2019-09-17 16:37 ` Alistair Francis 2019-09-17 16:37 ` [Qemu-riscv] " Alistair Francis 2019-09-20 22:40 ` Palmer Dabbelt 2019-07-03 8:40 ` [Qemu-devel] [PULL 05/32] RISC-V: Only Check PMP if MMU translation succeeds Palmer Dabbelt 2019-07-03 8:40 ` [Qemu-riscv] " Palmer Dabbelt 2019-07-03 8:40 ` [Qemu-devel] [PULL 06/32] RISC-V: Raise access fault exceptions on PMP violations Palmer Dabbelt 2019-07-03 8:40 ` [Qemu-riscv] " Palmer Dabbelt 2019-07-03 8:40 ` [Qemu-devel] [PULL 07/32] RISC-V: Check for the effective memory privilege mode during PMP checks Palmer Dabbelt 2019-07-03 8:40 ` [Qemu-riscv] " Palmer Dabbelt 2019-07-03 8:40 ` [Qemu-devel] [PULL 08/32] RISC-V: Check PMP during Page Table Walks Palmer Dabbelt 2019-07-03 8:40 ` [Qemu-riscv] " Palmer Dabbelt 2019-07-03 8:40 ` [Qemu-devel] [PULL 09/32] RISC-V: Fix a PMP bug where it succeeds even if PMP entry is off Palmer Dabbelt 2019-07-03 8:40 ` [Qemu-riscv] " Palmer Dabbelt 2019-07-03 8:40 ` [Qemu-devel] [PULL 10/32] RISC-V: Fix a PMP check with the correct access size Palmer Dabbelt 2019-07-03 8:40 ` [Qemu-riscv] " Palmer Dabbelt 2019-07-03 8:40 ` [Qemu-devel] [PULL 11/32] riscv: virt: Correct pci "bus-range" encoding Palmer Dabbelt 2019-07-03 8:40 ` [Qemu-riscv] " Palmer Dabbelt 2019-07-03 8:40 ` [Qemu-devel] [PULL 12/32] RISC-V: Fix a memory leak when realizing a sifive_e Palmer Dabbelt 2019-07-03 8:40 ` [Qemu-riscv] " Palmer Dabbelt 2019-07-03 8:40 ` [Qemu-devel] [PULL 13/32] target/riscv: Restructure deprecatd CPUs Palmer Dabbelt 2019-07-03 8:40 ` [Qemu-riscv] " Palmer Dabbelt 2019-07-03 8:40 ` [Qemu-devel] [PULL 14/32] target/riscv: Add the privledge spec version 1.11.0 Palmer Dabbelt 2019-07-03 8:40 ` [Qemu-riscv] " Palmer Dabbelt 2019-07-03 8:40 ` [Qemu-devel] [PULL 15/32] target/riscv: Add the mcountinhibit CSR Palmer Dabbelt 2019-07-03 8:40 ` [Qemu-riscv] " Palmer Dabbelt 2019-07-03 8:40 ` [Qemu-devel] [PULL 16/32] target/riscv: Set privledge spec 1.11.0 as default Palmer Dabbelt 2019-07-03 8:40 ` [Qemu-riscv] " Palmer Dabbelt 2019-07-03 8:40 ` [Qemu-devel] [PULL 17/32] qemu-deprecated.texi: Deprecate the RISC-V privledge spec 1.09.1 Palmer Dabbelt 2019-07-03 8:40 ` [Qemu-riscv] " Palmer Dabbelt 2019-07-03 8:40 ` [Qemu-devel] [PULL 18/32] target/riscv: Require either I or E base extension Palmer Dabbelt 2019-07-03 8:40 ` [Qemu-riscv] " Palmer Dabbelt 2019-07-03 8:40 ` [Qemu-devel] [PULL 19/32] target/riscv: Remove user version information Palmer Dabbelt 2019-07-03 8:40 ` [Qemu-riscv] " Palmer Dabbelt 2019-07-03 8:40 ` [Qemu-devel] [PULL 20/32] target/riscv: Add support for disabling/enabling Counters Palmer Dabbelt 2019-07-03 8:40 ` [Qemu-riscv] " Palmer Dabbelt 2019-07-03 8:40 ` [Qemu-devel] [PULL 21/32] RISC-V: Add support for the Zifencei extension Palmer Dabbelt 2019-07-03 8:40 ` [Qemu-riscv] " Palmer Dabbelt 2019-07-03 8:40 ` [Qemu-devel] [PULL 22/32] RISC-V: Add support for the Zicsr extension Palmer Dabbelt 2019-07-03 8:40 ` [Qemu-riscv] " Palmer Dabbelt 2019-07-03 8:40 ` [Qemu-devel] [PULL 23/32] RISC-V: Clear load reservations on context switch and SC Palmer Dabbelt 2019-07-03 8:40 ` [Qemu-riscv] " Palmer Dabbelt 2019-07-03 8:40 ` [Qemu-devel] [PULL 24/32] RISC-V: Update syscall list for 32-bit support Palmer Dabbelt 2019-07-03 8:40 ` [Qemu-riscv] " Palmer Dabbelt 2019-07-03 8:40 ` [Qemu-devel] [PULL 25/32] riscv: virt: Add cpu-topology DT node Palmer Dabbelt 2019-07-03 8:40 ` [Qemu-riscv] " Palmer Dabbelt 2019-07-03 8:40 ` [Qemu-devel] [PULL 26/32] disas/riscv: Disassemble reserved compressed encodings as illegal Palmer Dabbelt 2019-07-03 8:40 ` [Qemu-riscv] " Palmer Dabbelt 2019-07-03 8:40 ` Palmer Dabbelt [this message] 2019-07-03 8:40 ` [Qemu-riscv] [PULL 27/32] disas/riscv: Fix `rdinstreth` constraint Palmer Dabbelt 2019-07-03 8:40 ` [Qemu-devel] [PULL 28/32] riscv: sifive_u: Do not create hard-coded phandles in DT Palmer Dabbelt 2019-07-03 8:40 ` [Qemu-riscv] " Palmer Dabbelt 2019-07-03 8:40 ` [Qemu-devel] [PULL 29/32] riscv: sifive_u: Update the plic hart config to support multicore Palmer Dabbelt 2019-07-03 8:40 ` [Qemu-riscv] " Palmer Dabbelt 2019-07-03 8:40 ` [Qemu-devel] [PULL 30/32] hw/riscv: Split out the boot functions Palmer Dabbelt 2019-07-03 8:40 ` [Qemu-riscv] " Palmer Dabbelt 2019-07-03 8:40 ` [Qemu-devel] [PULL 31/32] hw/riscv: Add support for loading a firmware Palmer Dabbelt 2019-07-03 8:40 ` [Qemu-riscv] " Palmer Dabbelt 2019-07-03 8:40 ` [Qemu-devel] [PULL 32/32] hw/riscv: Extend the kernel loading support Palmer Dabbelt 2019-07-03 8:40 ` [Qemu-riscv] " Palmer Dabbelt 2019-07-04 10:40 ` [Qemu-devel] [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 v3 Peter Maydell 2019-07-04 10:40 ` [Qemu-riscv] " Peter Maydell
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