From: Peter Maydell <peter.maydell@linaro.org>
To: Palmer Dabbelt <palmer@sifive.com>
Cc: Alistair Francis <alistair23@gmail.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
"open list:RISC-V" <qemu-riscv@nongnu.org>,
QEMU Developers <qemu-devel@nongnu.org>
Subject: Re: [Qemu-devel] [PULL 04/32] target/riscv: Implement riscv_cpu_unassigned_access
Date: Fri, 16 Aug 2019 09:57:31 +0100 [thread overview]
Message-ID: <CAFEAcA_gpS3odPN_1sxCjV+0bRrNn+=xmS=5JgUFvz2A332LEw@mail.gmail.com> (raw)
In-Reply-To: <mhng-f7096b78-f11e-425e-8ade-d20c77ee1de6@palmer-si-x1e>
On Thu, 15 Aug 2019 at 23:17, Palmer Dabbelt <palmer@sifive.com> wrote:
> You're more than welcome to take them over. I've got something that boots
> Linux on my unassigned_access branch (github.com/palmer-dabbelt/qemu), but I
> haven't sanitized the whole port for physical accesses and I haven't convinced
> myself that my hook implementation is correct.
Rather than doing
if (retaddr) {
cpu_restore_state(cs, retaddr, true);
}
at the start of the hook I think you just want to pass 'retaddr'
as the final argument to riscv_raise_exception() instead of
using GETPC(). Other than that I think the hook itself is right.
The 'git grep' regexes in docs/devel/loads-stores.rst are handy
for finding the places where the target code is doing physical
accesses. IIRC the only ones I found with a quick scan were the
PTE loads in get_physical_address() via ldl_phys/ldq_phys, which will
now return 0 and run into the 'invalid PTE' code path. I don't
know whether your architecture requires some different behaviour
for bus errors on page table walk than that (you might want to
specifically code the error path anyway or comment it even if the
behaviour is right, to be a bit more explicit that it can happen).
thanks
-- PMM
WARNING: multiple messages have this Message-ID (diff)
From: Peter Maydell <peter.maydell@linaro.org>
To: Palmer Dabbelt <palmer@sifive.com>
Cc: Alistair Francis <alistair23@gmail.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
"open list:RISC-V" <qemu-riscv@nongnu.org>,
QEMU Developers <qemu-devel@nongnu.org>
Subject: Re: [Qemu-riscv] [Qemu-devel] [PULL 04/32] target/riscv: Implement riscv_cpu_unassigned_access
Date: Fri, 16 Aug 2019 09:57:31 +0100 [thread overview]
Message-ID: <CAFEAcA_gpS3odPN_1sxCjV+0bRrNn+=xmS=5JgUFvz2A332LEw@mail.gmail.com> (raw)
In-Reply-To: <mhng-f7096b78-f11e-425e-8ade-d20c77ee1de6@palmer-si-x1e>
On Thu, 15 Aug 2019 at 23:17, Palmer Dabbelt <palmer@sifive.com> wrote:
> You're more than welcome to take them over. I've got something that boots
> Linux on my unassigned_access branch (github.com/palmer-dabbelt/qemu), but I
> haven't sanitized the whole port for physical accesses and I haven't convinced
> myself that my hook implementation is correct.
Rather than doing
if (retaddr) {
cpu_restore_state(cs, retaddr, true);
}
at the start of the hook I think you just want to pass 'retaddr'
as the final argument to riscv_raise_exception() instead of
using GETPC(). Other than that I think the hook itself is right.
The 'git grep' regexes in docs/devel/loads-stores.rst are handy
for finding the places where the target code is doing physical
accesses. IIRC the only ones I found with a quick scan were the
PTE loads in get_physical_address() via ldl_phys/ldq_phys, which will
now return 0 and run into the 'invalid PTE' code path. I don't
know whether your architecture requires some different behaviour
for bus errors on page table walk than that (you might want to
specifically code the error path anyway or comment it even if the
behaviour is right, to be a bit more explicit that it can happen).
thanks
-- PMM
next prev parent reply other threads:[~2019-08-16 8:58 UTC|newest]
Thread overview: 83+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-03 8:40 [Qemu-devel] [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 v3 Palmer Dabbelt
2019-07-03 8:40 ` [Qemu-riscv] " Palmer Dabbelt
2019-07-03 8:40 ` [Qemu-devel] [PULL 01/32] target/riscv: Allow setting ISA extensions via CPU props Palmer Dabbelt
2019-07-03 8:40 ` [Qemu-riscv] " Palmer Dabbelt
2019-07-03 8:40 ` [Qemu-devel] [PULL 02/32] sifive_prci: Read and write PRCI registers Palmer Dabbelt
2019-07-03 8:40 ` [Qemu-riscv] " Palmer Dabbelt
2019-07-03 8:40 ` [Qemu-devel] [PULL 03/32] target/riscv: Fix PMP range boundary address bug Palmer Dabbelt
2019-07-03 8:40 ` [Qemu-riscv] " Palmer Dabbelt
2019-07-03 8:40 ` [Qemu-devel] [PULL 04/32] target/riscv: Implement riscv_cpu_unassigned_access Palmer Dabbelt
2019-07-03 8:40 ` [Qemu-riscv] " Palmer Dabbelt
2019-08-01 15:39 ` [Qemu-devel] " Peter Maydell
2019-08-01 15:39 ` [Qemu-riscv] " Peter Maydell
2019-08-13 22:44 ` [Qemu-devel] " Palmer Dabbelt
2019-08-13 22:44 ` [Qemu-riscv] " Palmer Dabbelt
2019-08-15 21:39 ` [Qemu-devel] " Alistair Francis
2019-08-15 21:39 ` [Qemu-riscv] " Alistair Francis
2019-08-15 22:17 ` Palmer Dabbelt
2019-08-15 22:17 ` [Qemu-riscv] " Palmer Dabbelt
2019-08-16 8:57 ` Peter Maydell [this message]
2019-08-16 8:57 ` Peter Maydell
2019-09-17 13:56 ` Peter Maydell
2019-09-17 13:56 ` [Qemu-riscv] " Peter Maydell
2019-09-17 16:37 ` Alistair Francis
2019-09-17 16:37 ` [Qemu-riscv] " Alistair Francis
2019-09-20 22:40 ` Palmer Dabbelt
2019-07-03 8:40 ` [Qemu-devel] [PULL 05/32] RISC-V: Only Check PMP if MMU translation succeeds Palmer Dabbelt
2019-07-03 8:40 ` [Qemu-riscv] " Palmer Dabbelt
2019-07-03 8:40 ` [Qemu-devel] [PULL 06/32] RISC-V: Raise access fault exceptions on PMP violations Palmer Dabbelt
2019-07-03 8:40 ` [Qemu-riscv] " Palmer Dabbelt
2019-07-03 8:40 ` [Qemu-devel] [PULL 07/32] RISC-V: Check for the effective memory privilege mode during PMP checks Palmer Dabbelt
2019-07-03 8:40 ` [Qemu-riscv] " Palmer Dabbelt
2019-07-03 8:40 ` [Qemu-devel] [PULL 08/32] RISC-V: Check PMP during Page Table Walks Palmer Dabbelt
2019-07-03 8:40 ` [Qemu-riscv] " Palmer Dabbelt
2019-07-03 8:40 ` [Qemu-devel] [PULL 09/32] RISC-V: Fix a PMP bug where it succeeds even if PMP entry is off Palmer Dabbelt
2019-07-03 8:40 ` [Qemu-riscv] " Palmer Dabbelt
2019-07-03 8:40 ` [Qemu-devel] [PULL 10/32] RISC-V: Fix a PMP check with the correct access size Palmer Dabbelt
2019-07-03 8:40 ` [Qemu-riscv] " Palmer Dabbelt
2019-07-03 8:40 ` [Qemu-devel] [PULL 11/32] riscv: virt: Correct pci "bus-range" encoding Palmer Dabbelt
2019-07-03 8:40 ` [Qemu-riscv] " Palmer Dabbelt
2019-07-03 8:40 ` [Qemu-devel] [PULL 12/32] RISC-V: Fix a memory leak when realizing a sifive_e Palmer Dabbelt
2019-07-03 8:40 ` [Qemu-riscv] " Palmer Dabbelt
2019-07-03 8:40 ` [Qemu-devel] [PULL 13/32] target/riscv: Restructure deprecatd CPUs Palmer Dabbelt
2019-07-03 8:40 ` [Qemu-riscv] " Palmer Dabbelt
2019-07-03 8:40 ` [Qemu-devel] [PULL 14/32] target/riscv: Add the privledge spec version 1.11.0 Palmer Dabbelt
2019-07-03 8:40 ` [Qemu-riscv] " Palmer Dabbelt
2019-07-03 8:40 ` [Qemu-devel] [PULL 15/32] target/riscv: Add the mcountinhibit CSR Palmer Dabbelt
2019-07-03 8:40 ` [Qemu-riscv] " Palmer Dabbelt
2019-07-03 8:40 ` [Qemu-devel] [PULL 16/32] target/riscv: Set privledge spec 1.11.0 as default Palmer Dabbelt
2019-07-03 8:40 ` [Qemu-riscv] " Palmer Dabbelt
2019-07-03 8:40 ` [Qemu-devel] [PULL 17/32] qemu-deprecated.texi: Deprecate the RISC-V privledge spec 1.09.1 Palmer Dabbelt
2019-07-03 8:40 ` [Qemu-riscv] " Palmer Dabbelt
2019-07-03 8:40 ` [Qemu-devel] [PULL 18/32] target/riscv: Require either I or E base extension Palmer Dabbelt
2019-07-03 8:40 ` [Qemu-riscv] " Palmer Dabbelt
2019-07-03 8:40 ` [Qemu-devel] [PULL 19/32] target/riscv: Remove user version information Palmer Dabbelt
2019-07-03 8:40 ` [Qemu-riscv] " Palmer Dabbelt
2019-07-03 8:40 ` [Qemu-devel] [PULL 20/32] target/riscv: Add support for disabling/enabling Counters Palmer Dabbelt
2019-07-03 8:40 ` [Qemu-riscv] " Palmer Dabbelt
2019-07-03 8:40 ` [Qemu-devel] [PULL 21/32] RISC-V: Add support for the Zifencei extension Palmer Dabbelt
2019-07-03 8:40 ` [Qemu-riscv] " Palmer Dabbelt
2019-07-03 8:40 ` [Qemu-devel] [PULL 22/32] RISC-V: Add support for the Zicsr extension Palmer Dabbelt
2019-07-03 8:40 ` [Qemu-riscv] " Palmer Dabbelt
2019-07-03 8:40 ` [Qemu-devel] [PULL 23/32] RISC-V: Clear load reservations on context switch and SC Palmer Dabbelt
2019-07-03 8:40 ` [Qemu-riscv] " Palmer Dabbelt
2019-07-03 8:40 ` [Qemu-devel] [PULL 24/32] RISC-V: Update syscall list for 32-bit support Palmer Dabbelt
2019-07-03 8:40 ` [Qemu-riscv] " Palmer Dabbelt
2019-07-03 8:40 ` [Qemu-devel] [PULL 25/32] riscv: virt: Add cpu-topology DT node Palmer Dabbelt
2019-07-03 8:40 ` [Qemu-riscv] " Palmer Dabbelt
2019-07-03 8:40 ` [Qemu-devel] [PULL 26/32] disas/riscv: Disassemble reserved compressed encodings as illegal Palmer Dabbelt
2019-07-03 8:40 ` [Qemu-riscv] " Palmer Dabbelt
2019-07-03 8:40 ` [Qemu-devel] [PULL 27/32] disas/riscv: Fix `rdinstreth` constraint Palmer Dabbelt
2019-07-03 8:40 ` [Qemu-riscv] " Palmer Dabbelt
2019-07-03 8:40 ` [Qemu-devel] [PULL 28/32] riscv: sifive_u: Do not create hard-coded phandles in DT Palmer Dabbelt
2019-07-03 8:40 ` [Qemu-riscv] " Palmer Dabbelt
2019-07-03 8:40 ` [Qemu-devel] [PULL 29/32] riscv: sifive_u: Update the plic hart config to support multicore Palmer Dabbelt
2019-07-03 8:40 ` [Qemu-riscv] " Palmer Dabbelt
2019-07-03 8:40 ` [Qemu-devel] [PULL 30/32] hw/riscv: Split out the boot functions Palmer Dabbelt
2019-07-03 8:40 ` [Qemu-riscv] " Palmer Dabbelt
2019-07-03 8:40 ` [Qemu-devel] [PULL 31/32] hw/riscv: Add support for loading a firmware Palmer Dabbelt
2019-07-03 8:40 ` [Qemu-riscv] " Palmer Dabbelt
2019-07-03 8:40 ` [Qemu-devel] [PULL 32/32] hw/riscv: Extend the kernel loading support Palmer Dabbelt
2019-07-03 8:40 ` [Qemu-riscv] " Palmer Dabbelt
2019-07-04 10:40 ` [Qemu-devel] [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 v3 Peter Maydell
2019-07-04 10:40 ` [Qemu-riscv] " Peter Maydell
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