From: "José Roberto de Souza" <jose.souza@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH 00/14] TGL TC enabling
Date: Fri, 13 Sep 2019 15:32:37 -0700 [thread overview]
Message-ID: <20190913223251.354877-1-jose.souza@intel.com> (raw)
This is all the patches required to have TC alt-mode working on TGL, no TBT or legacy support intented here but much of the work here will help those.
The dkl pll calculation is not 100% ready, so it is using the hardcoded table provided but even with this table it results in a port_clock state mismatch when running at 5.4Ghz.
Also I'm still debugging why enable clock gating after link training complete breaks all the following trainings.
All of above is noted in the respective commit message.
Other than the above the series is pretty much ready for reviews and testing.
Make sure you have firmware of TC retimers updated.
José Roberto de Souza (5):
drm/i915/tgl: Finish modular FIA support on registers
drm/i915/icl: Unify disable and enable phy clock gating functions
drm/i915/tgl: Fix dkl phy register space addressing
drm/i915/tgl: Check the UC health of tc controllers after power on
drm/i915: Add dkl phy pll calculations
Lucas De Marchi (2):
drm/i915/tgl: Add initial dkl pll support
drm/i915/tgl: initialize TC and TBT ports
Taylor, Clinton A (5):
drm/i915/tgl: Add missing ddi clock select during DP init sequence
drm/i915/tgl: TC helper function to return pin mapping
drm/i915/tgl: Fix driver crash when update_active_dpll is called
drm/i915/tgl: Add dkl phy programming sequences
drm/i915/tgl: Use dkl pll hardcoded values
Vandita Kulkarni (2):
drm/i915/tgl: Add dkl phy registers
drm/i915/tgl: Add support for dkl pll write
drivers/gpu/drm/i915/display/intel_ddi.c | 343 +++++++++++--
drivers/gpu/drm/i915/display/intel_display.c | 9 +-
.../drm/i915/display/intel_display_power.c | 16 +
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 456 +++++++++++++++++-
drivers/gpu/drm/i915/display/intel_tc.c | 64 ++-
drivers/gpu/drm/i915/display/intel_tc.h | 3 +
drivers/gpu/drm/i915/i915_drv.h | 3 +
drivers/gpu/drm/i915/i915_reg.h | 206 +++++++-
8 files changed, 1006 insertions(+), 94 deletions(-)
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next reply other threads:[~2019-09-13 22:32 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-13 22:32 José Roberto de Souza [this message]
2019-09-13 22:32 ` [PATCH 01/14] drm/i915/tgl: Add missing ddi clock select during DP init sequence José Roberto de Souza
2019-09-13 22:32 ` [PATCH 02/14] drm/i915/tgl: TC helper function to return pin mapping José Roberto de Souza
2019-09-14 5:54 ` Lucas De Marchi
2019-09-17 21:15 ` Souza, Jose
2019-09-13 22:32 ` [PATCH 03/14] drm/i915/tgl: Finish modular FIA support on registers José Roberto de Souza
2019-09-14 6:24 ` Lucas De Marchi
2019-09-18 1:08 ` Souza, Jose
2019-09-13 22:32 ` [PATCH 04/14] drm/i915/tgl: Fix driver crash when update_active_dpll is called José Roberto de Souza
2019-09-14 6:32 ` Lucas De Marchi
2019-09-17 22:59 ` Souza, Jose
2019-09-13 22:32 ` [PATCH 05/14] drm/i915/tgl: Add dkl phy registers José Roberto de Souza
2019-09-13 22:32 ` [PATCH 06/14] drm/i915/tgl: Add initial dkl pll support José Roberto de Souza
2019-09-13 22:32 ` [PATCH 07/14] drm/i915/tgl: Add support for dkl pll write José Roberto de Souza
2019-09-14 6:41 ` Lucas De Marchi
2019-09-16 8:48 ` Jani Nikula
2019-09-13 22:32 ` [PATCH 08/14] drm/i915/tgl: Add dkl phy programming sequences José Roberto de Souza
2019-09-13 22:32 ` [PATCH 09/14] drm/i915/icl: Unify disable and enable phy clock gating functions José Roberto de Souza
2019-09-13 22:32 ` [PATCH 10/14] drm/i915/tgl: Fix dkl phy register space addressing José Roberto de Souza
2019-09-14 7:26 ` Lucas De Marchi
2019-09-18 19:55 ` Souza, Jose
2019-09-13 22:32 ` [PATCH 11/14] drm/i915/tgl: Check the UC health of tc controllers after power on José Roberto de Souza
2019-09-13 22:32 ` [PATCH 12/14] drm/i915: Add dkl phy pll calculations José Roberto de Souza
2019-09-14 7:38 ` Lucas De Marchi
2019-09-13 22:32 ` [PATCH 13/14] drm/i915/tgl: Use dkl pll hardcoded values José Roberto de Souza
2019-09-13 22:32 ` [PATCH 14/14] drm/i915/tgl: initialize TC and TBT ports José Roberto de Souza
2019-09-13 22:53 ` ✗ Fi.CI.CHECKPATCH: warning for TGL TC enabling Patchwork
2019-09-13 23:12 ` ✓ Fi.CI.BAT: success " Patchwork
2019-09-15 7:07 ` ✓ Fi.CI.IGT: " Patchwork
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20190913223251.354877-1-jose.souza@intel.com \
--to=jose.souza@intel.com \
--cc=intel-gfx@lists.freedesktop.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.