From: "José Roberto de Souza" <jose.souza@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Subject: [PATCH CI 1/6] drm/i915/tgl: Add missing ddi clock select during DP init sequence
Date: Fri, 20 Sep 2019 13:58:05 -0700 [thread overview]
Message-ID: <20190920205810.211048-2-jose.souza@intel.com> (raw)
In-Reply-To: <20190920205810.211048-1-jose.souza@intel.com>
From: Clinton A Taylor <clinton.a.taylor@intel.com>
Step 4.b was complete missed because it is only required to TC and TBT.
Bspec: 49190
Reviewed-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Clinton A Taylor <clinton.a.taylor@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 0c0da9f6c2e8..dfd6b064cbc3 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3230,11 +3230,14 @@ static void tgl_ddi_pre_enable_dp(struct intel_encoder *encoder,
intel_edp_panel_on(intel_dp);
/*
- * 1.b, 3. and 4. is done before tgl_ddi_pre_enable_dp() by:
+ * 1.b, 3. and 4.a is done before tgl_ddi_pre_enable_dp() by:
* haswell_crtc_enable()->intel_encoders_pre_pll_enable() and
* haswell_crtc_enable()->intel_enable_shared_dpll()
*/
+ /* 4.b */
+ intel_ddi_clk_select(encoder, crtc_state);
+
/* 5. */
if (!intel_phy_is_tc(dev_priv, phy) ||
dig_port->tc_mode != TC_PORT_TBT_ALT)
--
2.23.0
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next prev parent reply other threads:[~2019-09-20 20:58 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-20 20:58 [PATCH CI 0/6] TGL TC enabling v2-CI José Roberto de Souza
2019-09-20 20:58 ` José Roberto de Souza [this message]
2019-09-20 20:58 ` [PATCH CI 2/6] drm/i915/tgl: Finish modular FIA support on registers José Roberto de Souza
2019-09-20 20:58 ` [PATCH CI 3/6] drm/i915/tgl/pll: Set update_active_dpll José Roberto de Souza
2019-09-20 20:58 ` [PATCH CI 4/6] drm/i915/tgl: Add dkl phy registers José Roberto de Souza
2019-09-20 20:58 ` [PATCH CI 5/6] drm/i915/icl: Unify disable and enable phy clock gating functions José Roberto de Souza
2019-09-20 20:58 ` [PATCH CI 6/6] drm/i915/tgl: Check the UC health of tc controllers after power on José Roberto de Souza
2019-09-20 22:02 ` ✗ Fi.CI.BAT: failure for TGL TC enabling v2-CI Patchwork
2019-09-20 23:21 ` ✓ Fi.CI.BAT: success for TGL TC enabling v2-CI (rev2) Patchwork
2019-09-22 13:56 ` ✓ Fi.CI.IGT: " Patchwork
2019-09-23 17:52 ` Souza, Jose
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