From: "José Roberto de Souza" <jose.souza@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Subject: [PATCH CI 3/6] drm/i915/tgl/pll: Set update_active_dpll
Date: Fri, 20 Sep 2019 13:58:07 -0700 [thread overview]
Message-ID: <20190920205810.211048-4-jose.souza@intel.com> (raw)
In-Reply-To: <20190920205810.211048-1-jose.souza@intel.com>
From: Clinton A Taylor <clinton.a.taylor@intel.com>
Commit 24a7bfe0c2d7 ("drm/i915: Keep the TypeC port mode fixed when the
port is active") added this new hook while in parallel TGL upstream was
happening and this was missed.
Without this driver will crash when TC DDI is added and driver is
preparing to do a full modeset.
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Clinton A Taylor <clinton.a.taylor@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 98288edf88f0..84e734d44828 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -3479,6 +3479,7 @@ static const struct intel_dpll_mgr tgl_pll_mgr = {
.dpll_info = tgl_plls,
.get_dplls = icl_get_dplls,
.put_dplls = icl_put_dplls,
+ .update_active_dpll = icl_update_active_dpll,
.dump_hw_state = icl_dump_hw_state,
};
--
2.23.0
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next prev parent reply other threads:[~2019-09-20 20:58 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-20 20:58 [PATCH CI 0/6] TGL TC enabling v2-CI José Roberto de Souza
2019-09-20 20:58 ` [PATCH CI 1/6] drm/i915/tgl: Add missing ddi clock select during DP init sequence José Roberto de Souza
2019-09-20 20:58 ` [PATCH CI 2/6] drm/i915/tgl: Finish modular FIA support on registers José Roberto de Souza
2019-09-20 20:58 ` José Roberto de Souza [this message]
2019-09-20 20:58 ` [PATCH CI 4/6] drm/i915/tgl: Add dkl phy registers José Roberto de Souza
2019-09-20 20:58 ` [PATCH CI 5/6] drm/i915/icl: Unify disable and enable phy clock gating functions José Roberto de Souza
2019-09-20 20:58 ` [PATCH CI 6/6] drm/i915/tgl: Check the UC health of tc controllers after power on José Roberto de Souza
2019-09-20 22:02 ` ✗ Fi.CI.BAT: failure for TGL TC enabling v2-CI Patchwork
2019-09-20 23:21 ` ✓ Fi.CI.BAT: success for TGL TC enabling v2-CI (rev2) Patchwork
2019-09-22 13:56 ` ✓ Fi.CI.IGT: " Patchwork
2019-09-23 17:52 ` Souza, Jose
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