From: Abel Vesa <abel.vesa@nxp.com> To: Leonard Crestez <leonard.crestez@nxp.com> Cc: "Stephen Boyd" <sboyd@kernel.org>, "MyungJoo Ham" <myungjoo.ham@samsung.com>, "Kyungmin Park" <kyungmin.park@samsung.com>, "Rob Herring" <robh+dt@kernel.org>, "Rafael J. Wysocki" <rjw@rjwysocki.net>, "Shawn Guo" <shawnguo@kernel.org>, "Chanwoo Choi" <cw00.choi@samsung.com>, "Mark Rutland" <mark.rutland@arm.com>, "Michael Turquette" <mturquette@baylibre.com>, "Artur Świgoń" <a.swigon@partner.samsung.com>, "Saravana Kannan" <saravanak@google.com>, "Angus Ainslie" <angus@akkea.ca>, "Martin Kepplinger" <martink@posteo.de>, "Matthias Kaehlcke" <mka@chromium.org>, "Krzysztof Kozlowski" <krzk@kernel.org>, "Alexandre Bailon" <abailon@baylibre.com>, "Georgi Djakov" <georgi.djakov@linaro.org>, "Aisheng Dong" <aisheng.dong@nxp.com>, "Jacky Bai" <ping.bai@nxp.com>, "Anson Huang" <anson.huang@nxp.com>, "Fabio Estevam" <fabio.estevam@nxp.com>, "Viresh Kumar" <viresh.kumar@linaro.org>, "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>, "linux-pm@vger.kernel.org" <linux-pm@vger.kernel.org>, "linux-clk@vger.kernel.org" <linux-clk@vger.kernel.org>, dl-linux-imx <linux-imx@nxp.com>, "kernel@pengutronix.de" <kernel@pengutronix.de>, "linux-arm-kernel@lists.infradead.org" <linux-arm-kernel@lists.infradead.org> Subject: Re: [PATCH v4 1/6] clk: imx8m: Set CLK_GET_RATE_NOCACHE on dram clocks Date: Tue, 12 Nov 2019 15:10:09 +0000 [thread overview] Message-ID: <20191112151008.5spfh7y5xzppk4s5@fsr-ub1664-175> (raw) In-Reply-To: <VI1PR04MB702387DCA9DB5A0A3F6288EDEE770@VI1PR04MB7023.eurprd04.prod.outlook.com> On 19-11-12 13:43:35, Leonard Crestez wrote: > On 12.11.2019 13:18, Abel Vesa wrote: > > On 19-11-09 00:39:51, Leonard Crestez wrote: > >> These clocks are only modified as part of DRAM frequency switches during > >> which DRAM itself is briefly inaccessible. The switch is performed with > >> a SMC call to by TF-A which runs from a SRAM area; upon returning to > >> linux several clocks bits are modified and we need to update them. > >> > >> For rate bits an easy solution is to just mark with > >> CLK_GET_RATE_NOCACHE so that new rates are always read back from > >> registers. > >> > >> Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> > >> --- > >> drivers/clk/imx/clk-imx8mm.c | 11 +++++++++-- > >> drivers/clk/imx/clk-imx8mn.c | 12 ++++++++++-- > >> drivers/clk/imx/clk-imx8mq.c | 15 +++++++++++---- > >> 3 files changed, 30 insertions(+), 8 deletions(-) > > >> --- a/drivers/clk/imx/clk-imx8mn.c > >> +++ b/drivers/clk/imx/clk-imx8mn.c > >> @@ -428,12 +428,20 @@ static int imx8mn_clocks_probe(struct platform_device *pdev) > >> clks[IMX8MN_CLK_AHB] = imx8m_clk_composite_critical("ahb", imx8mn_ahb_sels, base + 0x9000); > >> clks[IMX8MN_CLK_AUDIO_AHB] = imx8m_clk_composite("audio_ahb", imx8mn_audio_ahb_sels, base + 0x9100); > >> clks[IMX8MN_CLK_IPG_ROOT] = imx_clk_divider2("ipg_root", "ahb", base + 0x9080, 0, 1); > >> clks[IMX8MN_CLK_IPG_AUDIO_ROOT] = imx_clk_divider2("ipg_audio_root", "audio_ahb", base + 0x9180, 0, 1); > >> clks[IMX8MN_CLK_DRAM_CORE] = imx_clk_mux2_flags("dram_core_clk", base + 0x9800, 24, 1, imx8mn_dram_core_sels, ARRAY_SIZE(imx8mn_dram_core_sels), CLK_IS_CRITICAL); > >> - clks[IMX8MN_CLK_DRAM_ALT] = imx8m_clk_composite("dram_alt", imx8mn_dram_alt_sels, base + 0xa000); > >> - clks[IMX8MN_CLK_DRAM_APB] = imx8m_clk_composite_critical("dram_apb", imx8mn_dram_apb_sels, base + 0xa080); > >> + > >> + /* > >> + * DRAM clocks are manipulated from TF-A outside clock framework. > >> + * Mark with GET_RATE_NOCACHE to always read div value from hardware > >> + */ > >> + clks[IMX8MN_CLK_DRAM_ALT] = __imx8m_clk_composite("dram_alt", imx8mn_dram_alt_sels, base + 0xa000, > >> + CLK_GET_RATE_NOCACHE); > >> + clks[IMX8MN_CLK_DRAM_APB] = __imx8m_clk_composite("dram_apb", imx8mn_dram_apb_sels, base + 0xa080, > >> + CLK_IS_CRITICAL | CLK_GET_RATE_NOCACHE); > > > > nitpick: I think it looks better if we stick to one line each clock. > > I know it's against the 80 chars rule, but at least is consistent. > > Yes, there are longer lines in the imx8m* files anyway. > > If I fix this (in all instances) can I also add a "reviewed-by"? > Sorry, I forgot to add the line. For all the clock related changes: Reviewed-by: Abel Vesa <abel.vesa@nxp.com> > -- > Regards, > Leonard
WARNING: multiple messages have this Message-ID (diff)
From: Abel Vesa <abel.vesa@nxp.com> To: Leonard Crestez <leonard.crestez@nxp.com> Cc: "Mark Rutland" <mark.rutland@arm.com>, "Artur Świgoń" <a.swigon@partner.samsung.com>, "Jacky Bai" <ping.bai@nxp.com>, "Viresh Kumar" <viresh.kumar@linaro.org>, "Michael Turquette" <mturquette@baylibre.com>, "Angus Ainslie" <angus@akkea.ca>, "Alexandre Bailon" <abailon@baylibre.com>, "Matthias Kaehlcke" <mka@chromium.org>, "Saravana Kannan" <saravanak@google.com>, "Krzysztof Kozlowski" <krzk@kernel.org>, "linux-clk@vger.kernel.org" <linux-clk@vger.kernel.org>, "Chanwoo Choi" <cw00.choi@samsung.com>, "MyungJoo Ham" <myungjoo.ham@samsung.com>, dl-linux-imx <linux-imx@nxp.com>, "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>, "linux-pm@vger.kernel.org" <linux-pm@vger.kernel.org>, "Rob Herring" <robh+dt@kernel.org>, "Martin Kepplinger" <martink@posteo.de>, "linux-arm-kernel@lists.infradead.org" <linux-arm-kernel@lists.infradead.org>, "Aisheng Dong" <aisheng.dong@nxp.com>, "Anson Huang" <anson.huang@nxp.com>, "Stephen Boyd" <sboyd@kernel.org>, "Rafael J. Wysocki" <rjw@rjwysocki.net>, "Kyungmin Park" <kyungmin.park@samsung.com>, "kernel@pengutronix.de" <kernel@pengutronix.de>, "Fabio Estevam" <fabio.estevam@nxp.com>, "Shawn Guo" <shawnguo@kernel.org>, "Georgi Djakov" <georgi.djakov@linaro.org> Subject: Re: [PATCH v4 1/6] clk: imx8m: Set CLK_GET_RATE_NOCACHE on dram clocks Date: Tue, 12 Nov 2019 15:10:09 +0000 [thread overview] Message-ID: <20191112151008.5spfh7y5xzppk4s5@fsr-ub1664-175> (raw) In-Reply-To: <VI1PR04MB702387DCA9DB5A0A3F6288EDEE770@VI1PR04MB7023.eurprd04.prod.outlook.com> On 19-11-12 13:43:35, Leonard Crestez wrote: > On 12.11.2019 13:18, Abel Vesa wrote: > > On 19-11-09 00:39:51, Leonard Crestez wrote: > >> These clocks are only modified as part of DRAM frequency switches during > >> which DRAM itself is briefly inaccessible. The switch is performed with > >> a SMC call to by TF-A which runs from a SRAM area; upon returning to > >> linux several clocks bits are modified and we need to update them. > >> > >> For rate bits an easy solution is to just mark with > >> CLK_GET_RATE_NOCACHE so that new rates are always read back from > >> registers. > >> > >> Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> > >> --- > >> drivers/clk/imx/clk-imx8mm.c | 11 +++++++++-- > >> drivers/clk/imx/clk-imx8mn.c | 12 ++++++++++-- > >> drivers/clk/imx/clk-imx8mq.c | 15 +++++++++++---- > >> 3 files changed, 30 insertions(+), 8 deletions(-) > > >> --- a/drivers/clk/imx/clk-imx8mn.c > >> +++ b/drivers/clk/imx/clk-imx8mn.c > >> @@ -428,12 +428,20 @@ static int imx8mn_clocks_probe(struct platform_device *pdev) > >> clks[IMX8MN_CLK_AHB] = imx8m_clk_composite_critical("ahb", imx8mn_ahb_sels, base + 0x9000); > >> clks[IMX8MN_CLK_AUDIO_AHB] = imx8m_clk_composite("audio_ahb", imx8mn_audio_ahb_sels, base + 0x9100); > >> clks[IMX8MN_CLK_IPG_ROOT] = imx_clk_divider2("ipg_root", "ahb", base + 0x9080, 0, 1); > >> clks[IMX8MN_CLK_IPG_AUDIO_ROOT] = imx_clk_divider2("ipg_audio_root", "audio_ahb", base + 0x9180, 0, 1); > >> clks[IMX8MN_CLK_DRAM_CORE] = imx_clk_mux2_flags("dram_core_clk", base + 0x9800, 24, 1, imx8mn_dram_core_sels, ARRAY_SIZE(imx8mn_dram_core_sels), CLK_IS_CRITICAL); > >> - clks[IMX8MN_CLK_DRAM_ALT] = imx8m_clk_composite("dram_alt", imx8mn_dram_alt_sels, base + 0xa000); > >> - clks[IMX8MN_CLK_DRAM_APB] = imx8m_clk_composite_critical("dram_apb", imx8mn_dram_apb_sels, base + 0xa080); > >> + > >> + /* > >> + * DRAM clocks are manipulated from TF-A outside clock framework. > >> + * Mark with GET_RATE_NOCACHE to always read div value from hardware > >> + */ > >> + clks[IMX8MN_CLK_DRAM_ALT] = __imx8m_clk_composite("dram_alt", imx8mn_dram_alt_sels, base + 0xa000, > >> + CLK_GET_RATE_NOCACHE); > >> + clks[IMX8MN_CLK_DRAM_APB] = __imx8m_clk_composite("dram_apb", imx8mn_dram_apb_sels, base + 0xa080, > >> + CLK_IS_CRITICAL | CLK_GET_RATE_NOCACHE); > > > > nitpick: I think it looks better if we stick to one line each clock. > > I know it's against the 80 chars rule, but at least is consistent. > > Yes, there are longer lines in the imx8m* files anyway. > > If I fix this (in all instances) can I also add a "reviewed-by"? > Sorry, I forgot to add the line. For all the clock related changes: Reviewed-by: Abel Vesa <abel.vesa@nxp.com> > -- > Regards, > Leonard _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2019-11-12 15:10 UTC|newest] Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-11-08 22:39 [PATCH v4 0/6] PM / devfreq: Add dynamic scaling for imx8m ddr controller Leonard Crestez 2019-11-08 22:39 ` Leonard Crestez 2019-11-08 22:39 ` [PATCH v4 1/6] clk: imx8m: Set CLK_GET_RATE_NOCACHE on dram clocks Leonard Crestez 2019-11-08 22:39 ` Leonard Crestez 2019-11-12 11:18 ` Abel Vesa 2019-11-12 11:18 ` Abel Vesa 2019-11-12 13:43 ` Leonard Crestez 2019-11-12 13:43 ` Leonard Crestez 2019-11-12 15:10 ` Abel Vesa [this message] 2019-11-12 15:10 ` Abel Vesa 2019-11-08 22:39 ` [PATCH v4 2/6] clk: imx: Mark dram pll on 8mm and 8mn with CLK_GET_RATE_NOCACHE Leonard Crestez 2019-11-08 22:39 ` Leonard Crestez 2019-11-12 11:18 ` Abel Vesa 2019-11-12 11:18 ` Abel Vesa 2019-11-08 22:39 ` [PATCH v4 3/6] dt-bindings: memory: Add bindings for imx8m ddr controller Leonard Crestez 2019-11-08 22:39 ` Leonard Crestez 2019-11-08 22:39 ` [PATCH v4 4/6] PM / devfreq: Add dynamic scaling " Leonard Crestez 2019-11-08 22:39 ` Leonard Crestez 2019-11-11 3:23 ` Chanwoo Choi 2019-11-11 3:23 ` Chanwoo Choi 2019-11-11 17:23 ` Leonard Crestez 2019-11-11 17:23 ` Leonard Crestez 2019-11-12 1:00 ` Chanwoo Choi 2019-11-12 1:00 ` Chanwoo Choi 2019-11-12 14:47 ` Leonard Crestez 2019-11-12 14:47 ` Leonard Crestez 2019-11-08 22:39 ` [PATCH v4 5/6] PM / devfreq: imx8m-ddrc: Measure bandwidth with perf Leonard Crestez 2019-11-08 22:39 ` Leonard Crestez 2019-11-11 5:18 ` Chanwoo Choi 2019-11-11 5:18 ` Chanwoo Choi 2019-11-12 13:17 ` Leonard Crestez 2019-11-12 13:17 ` Leonard Crestez 2019-11-13 1:43 ` Chanwoo Choi 2019-11-13 1:43 ` Chanwoo Choi 2019-11-08 22:39 ` [PATCH v4 6/6] arm64: dts: imx8m: Add ddr controller nodes Leonard Crestez 2019-11-08 22:39 ` Leonard Crestez 2020-06-22 13:58 ` [PATCH v4 0/6] PM / devfreq: Add dynamic scaling for imx8m ddr controller Martin Kepplinger 2020-06-24 6:08 ` Leonard Crestez 2020-06-24 6:08 ` Leonard Crestez 2020-06-25 6:57 ` Martin Kepplinger 2020-06-25 6:57 ` Martin Kepplinger 2020-06-25 14:47 ` Abel Vesa 2020-06-25 14:47 ` Abel Vesa 2020-06-29 6:32 ` Martin Kepplinger 2020-06-29 6:32 ` Martin Kepplinger
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