From: Ville Syrjala <ville.syrjala@linux.intel.com> To: intel-gfx@lists.freedesktop.org Subject: [PATCH v2 05/14] drm/i915/fbc: Precompute gen9 cfb stride w/a Date: Wed, 27 Nov 2019 22:12:13 +0200 [thread overview] Message-ID: <20191127201222.16669-6-ville.syrjala@linux.intel.com> (raw) In-Reply-To: <20191127201222.16669-1-ville.syrjala@linux.intel.com> From: Ville Syrjälä <ville.syrjala@linux.intel.com> Precompute the override cfb stride value so that we can check it when determining if flip nuke can be used or not. The hardware has 13 bits for this, so we can shrink the storage to u16 while at it. v2: Don't explode when crtc_state->enable_fbc lies to us Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- drivers/gpu/drm/i915/display/intel_fbc.c | 38 +++++++++++++++--------- drivers/gpu/drm/i915/i915_drv.h | 3 +- 2 files changed, 26 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index eefa5a88b304..6a32f1eaefeb 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -283,8 +283,7 @@ static void gen7_fbc_activate(struct drm_i915_private *dev_priv) val &= ~(FBC_STRIDE_OVERRIDE | FBC_STRIDE_MASK); - if (i915_gem_object_get_tiling(params->vma->obj) != - I915_TILING_X) + if (params->gen9_wa_cfb_stride) val |= FBC_STRIDE_OVERRIDE | params->gen9_wa_cfb_stride; I915_WRITE(CHICKEN_MISC_4, val); @@ -414,8 +413,8 @@ static void intel_fbc_deactivate(struct drm_i915_private *dev_priv, static int find_compression_threshold(struct drm_i915_private *dev_priv, struct drm_mm_node *node, - int size, - int fb_cpp) + unsigned int size, + unsigned int fb_cpp) { int compression_threshold = 1; int ret; @@ -461,18 +460,15 @@ static int find_compression_threshold(struct drm_i915_private *dev_priv, } } -static int intel_fbc_alloc_cfb(struct intel_crtc *crtc) +static int intel_fbc_alloc_cfb(struct drm_i915_private *dev_priv, + unsigned int size, unsigned int fb_cpp) { - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); struct intel_fbc *fbc = &dev_priv->fbc; struct drm_mm_node *uninitialized_var(compressed_llb); - int size, fb_cpp, ret; + int ret; WARN_ON(drm_mm_node_allocated(&fbc->compressed_fb)); - size = intel_fbc_calculate_cfb_size(dev_priv, &fbc->state_cache); - fb_cpp = fbc->state_cache.fb.format->cpp[0]; - ret = find_compression_threshold(dev_priv, &fbc->compressed_fb, size, fb_cpp); if (!ret) @@ -823,9 +819,7 @@ static void intel_fbc_get_reg_params(struct intel_crtc *crtc, params->cfb_size = intel_fbc_calculate_cfb_size(dev_priv, cache); - if (IS_GEN(dev_priv, 9) && !IS_GEMINILAKE(dev_priv)) - params->gen9_wa_cfb_stride = DIV_ROUND_UP(cache->plane.src_w, - 32 * fbc->threshold) * 8; + params->gen9_wa_cfb_stride = cache->gen9_wa_cfb_stride; } void intel_fbc_pre_update(struct intel_crtc *crtc, @@ -1054,6 +1048,8 @@ void intel_fbc_enable(struct intel_crtc *crtc, { struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); struct intel_fbc *fbc = &dev_priv->fbc; + struct intel_fbc_state_cache *cache = &fbc->state_cache; + const struct drm_framebuffer *fb = plane_state->hw.fb; if (!fbc_supported(dev_priv)) return; @@ -1076,11 +1072,25 @@ void intel_fbc_enable(struct intel_crtc *crtc, WARN_ON(fbc->crtc != NULL); intel_fbc_update_state_cache(crtc, crtc_state, plane_state); - if (intel_fbc_alloc_cfb(crtc)) { + + /* FIXME crtc_state->enable_fbc lies :( */ + if (!cache->plane.visible) + goto out; + + if (intel_fbc_alloc_cfb(dev_priv, + intel_fbc_calculate_cfb_size(dev_priv, cache), + fb->format->cpp[0])) { fbc->no_fbc_reason = "not enough stolen memory"; goto out; } + if (IS_GEN(dev_priv, 9) && !IS_GEMINILAKE(dev_priv) && + fb->modifier != I915_FORMAT_MOD_X_TILED) + cache->gen9_wa_cfb_stride = + DIV_ROUND_UP(cache->plane.src_w, 32 * fbc->threshold) * 8; + else + cache->gen9_wa_cfb_stride = 0; + DRM_DEBUG_KMS("Enabling FBC on pipe %c\n", pipe_name(crtc->pipe)); fbc->no_fbc_reason = "FBC enabled but not active yet\n"; diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index d0e00078fbce..ccde7eaf7dab 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -417,6 +417,7 @@ struct intel_fbc { const struct drm_format_info *format; unsigned int stride; } fb; + u16 gen9_wa_cfb_stride; } state_cache; /* @@ -442,7 +443,7 @@ struct intel_fbc { } fb; int cfb_size; - unsigned int gen9_wa_cfb_stride; + u16 gen9_wa_cfb_stride; } params; const char *no_fbc_reason; -- 2.23.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
WARNING: multiple messages have this Message-ID (diff)
From: Ville Syrjala <ville.syrjala@linux.intel.com> To: intel-gfx@lists.freedesktop.org Subject: [Intel-gfx] [PATCH v2 05/14] drm/i915/fbc: Precompute gen9 cfb stride w/a Date: Wed, 27 Nov 2019 22:12:13 +0200 [thread overview] Message-ID: <20191127201222.16669-6-ville.syrjala@linux.intel.com> (raw) Message-ID: <20191127201213.SWjFW-fUveNUFIcy62P_Xk2GmA3jgivTUDbTW6If2Kw@z> (raw) In-Reply-To: <20191127201222.16669-1-ville.syrjala@linux.intel.com> From: Ville Syrjälä <ville.syrjala@linux.intel.com> Precompute the override cfb stride value so that we can check it when determining if flip nuke can be used or not. The hardware has 13 bits for this, so we can shrink the storage to u16 while at it. v2: Don't explode when crtc_state->enable_fbc lies to us Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- drivers/gpu/drm/i915/display/intel_fbc.c | 38 +++++++++++++++--------- drivers/gpu/drm/i915/i915_drv.h | 3 +- 2 files changed, 26 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index eefa5a88b304..6a32f1eaefeb 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -283,8 +283,7 @@ static void gen7_fbc_activate(struct drm_i915_private *dev_priv) val &= ~(FBC_STRIDE_OVERRIDE | FBC_STRIDE_MASK); - if (i915_gem_object_get_tiling(params->vma->obj) != - I915_TILING_X) + if (params->gen9_wa_cfb_stride) val |= FBC_STRIDE_OVERRIDE | params->gen9_wa_cfb_stride; I915_WRITE(CHICKEN_MISC_4, val); @@ -414,8 +413,8 @@ static void intel_fbc_deactivate(struct drm_i915_private *dev_priv, static int find_compression_threshold(struct drm_i915_private *dev_priv, struct drm_mm_node *node, - int size, - int fb_cpp) + unsigned int size, + unsigned int fb_cpp) { int compression_threshold = 1; int ret; @@ -461,18 +460,15 @@ static int find_compression_threshold(struct drm_i915_private *dev_priv, } } -static int intel_fbc_alloc_cfb(struct intel_crtc *crtc) +static int intel_fbc_alloc_cfb(struct drm_i915_private *dev_priv, + unsigned int size, unsigned int fb_cpp) { - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); struct intel_fbc *fbc = &dev_priv->fbc; struct drm_mm_node *uninitialized_var(compressed_llb); - int size, fb_cpp, ret; + int ret; WARN_ON(drm_mm_node_allocated(&fbc->compressed_fb)); - size = intel_fbc_calculate_cfb_size(dev_priv, &fbc->state_cache); - fb_cpp = fbc->state_cache.fb.format->cpp[0]; - ret = find_compression_threshold(dev_priv, &fbc->compressed_fb, size, fb_cpp); if (!ret) @@ -823,9 +819,7 @@ static void intel_fbc_get_reg_params(struct intel_crtc *crtc, params->cfb_size = intel_fbc_calculate_cfb_size(dev_priv, cache); - if (IS_GEN(dev_priv, 9) && !IS_GEMINILAKE(dev_priv)) - params->gen9_wa_cfb_stride = DIV_ROUND_UP(cache->plane.src_w, - 32 * fbc->threshold) * 8; + params->gen9_wa_cfb_stride = cache->gen9_wa_cfb_stride; } void intel_fbc_pre_update(struct intel_crtc *crtc, @@ -1054,6 +1048,8 @@ void intel_fbc_enable(struct intel_crtc *crtc, { struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); struct intel_fbc *fbc = &dev_priv->fbc; + struct intel_fbc_state_cache *cache = &fbc->state_cache; + const struct drm_framebuffer *fb = plane_state->hw.fb; if (!fbc_supported(dev_priv)) return; @@ -1076,11 +1072,25 @@ void intel_fbc_enable(struct intel_crtc *crtc, WARN_ON(fbc->crtc != NULL); intel_fbc_update_state_cache(crtc, crtc_state, plane_state); - if (intel_fbc_alloc_cfb(crtc)) { + + /* FIXME crtc_state->enable_fbc lies :( */ + if (!cache->plane.visible) + goto out; + + if (intel_fbc_alloc_cfb(dev_priv, + intel_fbc_calculate_cfb_size(dev_priv, cache), + fb->format->cpp[0])) { fbc->no_fbc_reason = "not enough stolen memory"; goto out; } + if (IS_GEN(dev_priv, 9) && !IS_GEMINILAKE(dev_priv) && + fb->modifier != I915_FORMAT_MOD_X_TILED) + cache->gen9_wa_cfb_stride = + DIV_ROUND_UP(cache->plane.src_w, 32 * fbc->threshold) * 8; + else + cache->gen9_wa_cfb_stride = 0; + DRM_DEBUG_KMS("Enabling FBC on pipe %c\n", pipe_name(crtc->pipe)); fbc->no_fbc_reason = "FBC enabled but not active yet\n"; diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index d0e00078fbce..ccde7eaf7dab 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -417,6 +417,7 @@ struct intel_fbc { const struct drm_format_info *format; unsigned int stride; } fb; + u16 gen9_wa_cfb_stride; } state_cache; /* @@ -442,7 +443,7 @@ struct intel_fbc { } fb; int cfb_size; - unsigned int gen9_wa_cfb_stride; + u16 gen9_wa_cfb_stride; } params; const char *no_fbc_reason; -- 2.23.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2019-11-27 20:12 UTC|newest] Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-11-27 20:12 [PATCH v2 00/14] drm/i915/fbc: Fix FBC for glk+ Ville Syrjala 2019-11-27 20:12 ` [Intel-gfx] " Ville Syrjala 2019-11-27 20:12 ` [PATCH v2 01/14] drm/i915/fbc: Disable fbc by default on all glk+ Ville Syrjala 2019-11-27 20:12 ` [Intel-gfx] " Ville Syrjala 2019-11-29 18:34 ` Sasha Levin 2019-11-29 18:34 ` [Intel-gfx] " Sasha Levin 2019-11-27 20:12 ` [PATCH v2 02/14] drm/i915/fbc: Nuke bogus single pipe fbc1 restriction Ville Syrjala 2019-11-27 20:12 ` [Intel-gfx] " Ville Syrjala 2019-11-27 20:12 ` [PATCH v2 03/14] drm/i915: Relocate intel_crtc_active() Ville Syrjala 2019-11-27 20:12 ` [Intel-gfx] " Ville Syrjala 2019-11-27 20:12 ` [PATCH v2 04/14] drm/i915/fbc: Remove the FBC_RT_BASE setup for ILK/SNB Ville Syrjala 2019-11-27 20:12 ` [Intel-gfx] " Ville Syrjala 2019-11-27 20:12 ` Ville Syrjala [this message] 2019-11-27 20:12 ` [Intel-gfx] [PATCH v2 05/14] drm/i915/fbc: Precompute gen9 cfb stride w/a Ville Syrjala 2019-11-27 20:12 ` [PATCH v2 06/14] drm/i915/fbc: Track plane visibility Ville Syrjala 2019-11-27 20:12 ` [Intel-gfx] " Ville Syrjala 2019-11-27 20:12 ` [PATCH v2 07/14] drm/i915/fbc: Store fence_id direction in fbc cache/params Ville Syrjala 2019-11-27 20:12 ` [Intel-gfx] " Ville Syrjala 2019-11-27 20:12 ` [PATCH v2 08/14] drm/i915/fbc: Make fence_id optional for i965gm Ville Syrjala 2019-11-27 20:12 ` [Intel-gfx] " Ville Syrjala 2019-11-27 20:12 ` [PATCH v2 09/14] drm/i915/fbc: s/gen9 && !glk/gen9_bc || bxt/ Ville Syrjala 2019-11-27 20:12 ` [Intel-gfx] " Ville Syrjala 2019-11-27 20:12 ` [PATCH v2 10/14] drm/i915/fbc: Nuke fbc.enabled Ville Syrjala 2019-11-27 20:12 ` [Intel-gfx] " Ville Syrjala 2019-11-27 20:12 ` [PATCH v2 11/14] drm/i915/fbc: Start using flip nuke Ville Syrjala 2019-11-27 20:12 ` [Intel-gfx] " Ville Syrjala 2019-11-27 20:12 ` [PATCH v2 12/14] drm/i915/fbc: Wait for vblank after FBC disable on glk+ Ville Syrjala 2019-11-27 20:12 ` [Intel-gfx] " Ville Syrjala 2019-11-28 15:03 ` [PATCH v3 " Ville Syrjala 2019-11-28 15:03 ` [Intel-gfx] " Ville Syrjala 2019-11-27 20:12 ` [PATCH v2 13/14] drm/i915/fbc: Enable fbc by default on glk+ once again Ville Syrjala 2019-11-27 20:12 ` [Intel-gfx] " Ville Syrjala 2019-11-27 20:12 ` [PATCH v2 14/14] drm/i915/fbc: Reallocate cfb if we need more of it Ville Syrjala 2019-11-27 20:12 ` [Intel-gfx] " Ville Syrjala 2019-11-28 15:48 ` Maarten Lankhorst 2019-11-28 15:48 ` [Intel-gfx] " Maarten Lankhorst 2019-11-28 15:59 ` Ville Syrjälä 2019-11-28 15:59 ` [Intel-gfx] " Ville Syrjälä 2019-11-29 8:48 ` Maarten Lankhorst 2019-11-29 8:48 ` [Intel-gfx] " Maarten Lankhorst 2019-11-29 11:37 ` Ville Syrjälä 2019-11-29 11:37 ` [Intel-gfx] " Ville Syrjälä 2019-12-03 8:45 ` Maarten Lankhorst 2019-12-03 8:45 ` [Intel-gfx] " Maarten Lankhorst 2019-12-03 13:04 ` Ville Syrjälä 2019-12-09 14:17 ` Ville Syrjälä 2019-11-27 23:15 ` ✗ Fi.CI.BAT: failure for drm/i915/fbc: Fix FBC for glk+ (rev4) Patchwork 2019-11-27 23:15 ` [Intel-gfx] " Patchwork 2019-11-28 1:33 ` [PATCH v2 00/14] drm/i915/fbc: Fix FBC for glk+ Daniel Drake 2019-11-28 1:33 ` [Intel-gfx] " Daniel Drake 2019-11-28 18:02 ` ✓ Fi.CI.BAT: success for drm/i915/fbc: Fix FBC for glk+ (rev5) Patchwork 2019-11-28 18:02 ` [Intel-gfx] " Patchwork 2019-11-29 23:51 ` ✓ Fi.CI.IGT: " Patchwork 2019-11-29 23:51 ` [Intel-gfx] " Patchwork
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