From: Zhiqiang Hou <Zhiqiang.Hou@nxp.com> To: linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, bhelgaas@google.com, robh+dt@kernel.org, andrew.murray@arm.com, arnd@arndb.de, mark.rutland@arm.com, l.subrahmanya@mobiveil.co.in, shawnguo@kernel.org, m.karthikeyan@mobiveil.co.in, leoyang.li@nxp.com, lorenzo.pieralisi@arm.com, catalin.marinas@arm.com, will.deacon@arm.com Cc: Mingkai.Hu@nxp.com, Minghuan.Lian@nxp.com, Xiaowei.Bao@nxp.com, Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Subject: [PATCHv10 03/13] PCI: mobiveil: Collect the interrupt related operations into a function Date: Thu, 13 Feb 2020 12:06:34 +0800 [thread overview] Message-ID: <20200213040644.45858-4-Zhiqiang.Hou@nxp.com> (raw) In-Reply-To: <20200213040644.45858-1-Zhiqiang.Hou@nxp.com> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Collect the interrupt initialization related operations into a new function such that it is more readable. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> --- V10: - Refined the subject and change log. drivers/pci/controller/pcie-mobiveil.c | 65 +++++++++++++++++--------- 1 file changed, 42 insertions(+), 23 deletions(-) diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controller/pcie-mobiveil.c index 01df04ea5b48..9449528bb14f 100644 --- a/drivers/pci/controller/pcie-mobiveil.c +++ b/drivers/pci/controller/pcie-mobiveil.c @@ -454,12 +454,6 @@ static int mobiveil_pcie_parse_dt(struct mobiveil_pcie *pcie) return PTR_ERR(pcie->csr_axi_slave_base); pcie->pcie_reg_base = res->start; - /* map MSI config resource */ - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "apb_csr"); - pcie->apb_csr_base = devm_pci_remap_cfg_resource(dev, res); - if (IS_ERR(pcie->apb_csr_base)) - return PTR_ERR(pcie->apb_csr_base); - /* read the number of windows requested */ if (of_property_read_u32(node, "apio-wins", &pcie->apio_wins)) pcie->apio_wins = MAX_PIO_WINDOWS; @@ -467,12 +461,6 @@ static int mobiveil_pcie_parse_dt(struct mobiveil_pcie *pcie) if (of_property_read_u32(node, "ppio-wins", &pcie->ppio_wins)) pcie->ppio_wins = MAX_PIO_WINDOWS; - rp->irq = platform_get_irq(pdev, 0); - if (rp->irq <= 0) { - dev_err(dev, "failed to map IRQ: %d\n", rp->irq); - return -ENODEV; - } - return 0; } @@ -618,9 +606,6 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie) pab_ctrl |= (1 << AMBA_PIO_ENABLE_SHIFT) | (1 << PEX_PIO_ENABLE_SHIFT); mobiveil_csr_writel(pcie, pab_ctrl, PAB_CTRL); - mobiveil_csr_writel(pcie, (PAB_INTP_INTX_MASK | PAB_INTP_MSI_MASK), - PAB_INTP_AMBA_MISC_ENB); - /* * program PIO Enable Bit to 1 and Config Window Enable Bit to 1 in * PAB_AXI_PIO_CTRL Register @@ -670,9 +655,6 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie) value |= (PCI_CLASS_BRIDGE_PCI << 16); mobiveil_csr_writel(pcie, value, PAB_INTP_AXI_PIO_CLASS); - /* setup MSI hardware registers */ - mobiveil_pcie_enable_msi(pcie); - return 0; } @@ -873,6 +855,46 @@ static int mobiveil_pcie_init_irq_domain(struct mobiveil_pcie *pcie) return 0; } +static int mobiveil_pcie_interrupt_init(struct mobiveil_pcie *pcie) +{ + struct platform_device *pdev = pcie->pdev; + struct device *dev = &pdev->dev; + struct mobiveil_root_port *rp = &pcie->rp; + struct resource *res; + int ret; + + /* map MSI config resource */ + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "apb_csr"); + pcie->apb_csr_base = devm_pci_remap_cfg_resource(dev, res); + if (IS_ERR(pcie->apb_csr_base)) + return PTR_ERR(pcie->apb_csr_base); + + /* setup MSI hardware registers */ + mobiveil_pcie_enable_msi(pcie); + + rp->irq = platform_get_irq(pdev, 0); + if (rp->irq <= 0) { + dev_err(dev, "failed to map IRQ: %d\n", rp->irq); + return -ENODEV; + } + + /* initialize the IRQ domains */ + ret = mobiveil_pcie_init_irq_domain(pcie); + if (ret) { + dev_err(dev, "Failed creating IRQ Domain\n"); + return ret; + } + + irq_set_chained_handler_and_data(rp->irq, mobiveil_pcie_isr, pcie); + + /* Enable interrupts */ + mobiveil_csr_writel(pcie, (PAB_INTP_INTX_MASK | PAB_INTP_MSI_MASK), + PAB_INTP_AMBA_MISC_ENB); + + + return 0; +} + static int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie) { struct mobiveil_root_port *rp = &pcie->rp; @@ -906,15 +928,12 @@ static int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie) return ret; } - /* initialize the IRQ domains */ - ret = mobiveil_pcie_init_irq_domain(pcie); + ret = mobiveil_pcie_interrupt_init(pcie); if (ret) { - dev_err(dev, "Failed creating IRQ Domain\n"); + dev_err(dev, "Interrupt init failed\n"); return ret; } - irq_set_chained_handler_and_data(rp->irq, mobiveil_pcie_isr, pcie); - /* Initialize bridge */ bridge->dev.parent = dev; bridge->sysdata = pcie; -- 2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: Zhiqiang Hou <Zhiqiang.Hou@nxp.com> To: linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, bhelgaas@google.com, robh+dt@kernel.org, andrew.murray@arm.com, arnd@arndb.de, mark.rutland@arm.com, l.subrahmanya@mobiveil.co.in, shawnguo@kernel.org, m.karthikeyan@mobiveil.co.in, leoyang.li@nxp.com, lorenzo.pieralisi@arm.com, catalin.marinas@arm.com, will.deacon@arm.com Cc: Minghuan.Lian@nxp.com, Hou Zhiqiang <Zhiqiang.Hou@nxp.com>, Xiaowei.Bao@nxp.com, Mingkai.Hu@nxp.com Subject: [PATCHv10 03/13] PCI: mobiveil: Collect the interrupt related operations into a function Date: Thu, 13 Feb 2020 12:06:34 +0800 [thread overview] Message-ID: <20200213040644.45858-4-Zhiqiang.Hou@nxp.com> (raw) In-Reply-To: <20200213040644.45858-1-Zhiqiang.Hou@nxp.com> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Collect the interrupt initialization related operations into a new function such that it is more readable. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> --- V10: - Refined the subject and change log. drivers/pci/controller/pcie-mobiveil.c | 65 +++++++++++++++++--------- 1 file changed, 42 insertions(+), 23 deletions(-) diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controller/pcie-mobiveil.c index 01df04ea5b48..9449528bb14f 100644 --- a/drivers/pci/controller/pcie-mobiveil.c +++ b/drivers/pci/controller/pcie-mobiveil.c @@ -454,12 +454,6 @@ static int mobiveil_pcie_parse_dt(struct mobiveil_pcie *pcie) return PTR_ERR(pcie->csr_axi_slave_base); pcie->pcie_reg_base = res->start; - /* map MSI config resource */ - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "apb_csr"); - pcie->apb_csr_base = devm_pci_remap_cfg_resource(dev, res); - if (IS_ERR(pcie->apb_csr_base)) - return PTR_ERR(pcie->apb_csr_base); - /* read the number of windows requested */ if (of_property_read_u32(node, "apio-wins", &pcie->apio_wins)) pcie->apio_wins = MAX_PIO_WINDOWS; @@ -467,12 +461,6 @@ static int mobiveil_pcie_parse_dt(struct mobiveil_pcie *pcie) if (of_property_read_u32(node, "ppio-wins", &pcie->ppio_wins)) pcie->ppio_wins = MAX_PIO_WINDOWS; - rp->irq = platform_get_irq(pdev, 0); - if (rp->irq <= 0) { - dev_err(dev, "failed to map IRQ: %d\n", rp->irq); - return -ENODEV; - } - return 0; } @@ -618,9 +606,6 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie) pab_ctrl |= (1 << AMBA_PIO_ENABLE_SHIFT) | (1 << PEX_PIO_ENABLE_SHIFT); mobiveil_csr_writel(pcie, pab_ctrl, PAB_CTRL); - mobiveil_csr_writel(pcie, (PAB_INTP_INTX_MASK | PAB_INTP_MSI_MASK), - PAB_INTP_AMBA_MISC_ENB); - /* * program PIO Enable Bit to 1 and Config Window Enable Bit to 1 in * PAB_AXI_PIO_CTRL Register @@ -670,9 +655,6 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie) value |= (PCI_CLASS_BRIDGE_PCI << 16); mobiveil_csr_writel(pcie, value, PAB_INTP_AXI_PIO_CLASS); - /* setup MSI hardware registers */ - mobiveil_pcie_enable_msi(pcie); - return 0; } @@ -873,6 +855,46 @@ static int mobiveil_pcie_init_irq_domain(struct mobiveil_pcie *pcie) return 0; } +static int mobiveil_pcie_interrupt_init(struct mobiveil_pcie *pcie) +{ + struct platform_device *pdev = pcie->pdev; + struct device *dev = &pdev->dev; + struct mobiveil_root_port *rp = &pcie->rp; + struct resource *res; + int ret; + + /* map MSI config resource */ + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "apb_csr"); + pcie->apb_csr_base = devm_pci_remap_cfg_resource(dev, res); + if (IS_ERR(pcie->apb_csr_base)) + return PTR_ERR(pcie->apb_csr_base); + + /* setup MSI hardware registers */ + mobiveil_pcie_enable_msi(pcie); + + rp->irq = platform_get_irq(pdev, 0); + if (rp->irq <= 0) { + dev_err(dev, "failed to map IRQ: %d\n", rp->irq); + return -ENODEV; + } + + /* initialize the IRQ domains */ + ret = mobiveil_pcie_init_irq_domain(pcie); + if (ret) { + dev_err(dev, "Failed creating IRQ Domain\n"); + return ret; + } + + irq_set_chained_handler_and_data(rp->irq, mobiveil_pcie_isr, pcie); + + /* Enable interrupts */ + mobiveil_csr_writel(pcie, (PAB_INTP_INTX_MASK | PAB_INTP_MSI_MASK), + PAB_INTP_AMBA_MISC_ENB); + + + return 0; +} + static int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie) { struct mobiveil_root_port *rp = &pcie->rp; @@ -906,15 +928,12 @@ static int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie) return ret; } - /* initialize the IRQ domains */ - ret = mobiveil_pcie_init_irq_domain(pcie); + ret = mobiveil_pcie_interrupt_init(pcie); if (ret) { - dev_err(dev, "Failed creating IRQ Domain\n"); + dev_err(dev, "Interrupt init failed\n"); return ret; } - irq_set_chained_handler_and_data(rp->irq, mobiveil_pcie_isr, pcie); - /* Initialize bridge */ bridge->dev.parent = dev; bridge->sysdata = pcie; -- 2.17.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-02-13 4:10 UTC|newest] Thread overview: 76+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-02-13 4:06 [PATCHv10 00/13] PCI: Recode Mobiveil driver and add PCIe Gen4 driver for NXP Layerscape SoCs Zhiqiang Hou 2020-02-13 4:06 ` Zhiqiang Hou 2020-02-13 4:06 ` [PATCHv10 01/13] PCI: mobiveil: Introduce a new structure mobiveil_root_port Zhiqiang Hou 2020-02-13 4:06 ` Zhiqiang Hou 2020-02-20 17:12 ` Andrew Murray 2020-02-20 17:12 ` Andrew Murray 2020-02-24 5:45 ` Z.q. Hou 2020-02-24 5:45 ` Z.q. Hou 2020-02-13 4:06 ` [PATCHv10 02/13] PCI: mobiveil: Move the host initialization into a function Zhiqiang Hou 2020-02-13 4:06 ` Zhiqiang Hou 2020-02-20 17:19 ` Andrew Murray 2020-02-20 17:19 ` Andrew Murray 2020-02-24 5:48 ` Z.q. Hou 2020-02-24 5:48 ` Z.q. Hou 2020-02-21 12:15 ` Lorenzo Pieralisi 2020-02-21 12:15 ` Lorenzo Pieralisi 2020-02-13 4:06 ` Zhiqiang Hou [this message] 2020-02-13 4:06 ` [PATCHv10 03/13] PCI: mobiveil: Collect the interrupt related operations " Zhiqiang Hou 2020-02-20 17:23 ` Andrew Murray 2020-02-20 17:23 ` Andrew Murray 2020-02-24 5:49 ` Z.q. Hou 2020-02-24 5:49 ` Z.q. Hou 2020-02-13 4:06 ` [PATCHv10 04/13] PCI: mobiveil: Modularize the Mobiveil PCIe Host Bridge IP driver Zhiqiang Hou 2020-02-13 4:06 ` Zhiqiang Hou 2020-02-13 4:06 ` [PATCHv10 05/13] PCI: mobiveil: Add callback function for interrupt initialization Zhiqiang Hou 2020-02-13 4:06 ` Zhiqiang Hou 2020-02-20 17:25 ` Andrew Murray 2020-02-20 17:25 ` Andrew Murray 2020-02-24 5:49 ` Z.q. Hou 2020-02-24 5:49 ` Z.q. Hou 2020-02-13 4:06 ` [PATCHv10 06/13] PCI: mobiveil: Add callback function for link up check Zhiqiang Hou 2020-02-13 4:06 ` Zhiqiang Hou 2020-02-13 4:06 ` [PATCHv10 07/13] PCI: mobiveil: Allow mobiveil_host_init() to be used to re-init host Zhiqiang Hou 2020-02-13 4:06 ` Zhiqiang Hou 2020-02-20 17:28 ` Andrew Murray 2020-02-20 17:28 ` Andrew Murray 2020-02-24 5:49 ` Z.q. Hou 2020-02-24 5:49 ` Z.q. Hou 2020-02-13 4:06 ` [PATCHv10 08/13] PCI: mobiveil: Add 8-bit and 16-bit CSR register accessors Zhiqiang Hou 2020-02-13 4:06 ` Zhiqiang Hou 2020-02-20 17:29 ` Andrew Murray 2020-02-20 17:29 ` Andrew Murray 2020-02-24 5:50 ` Z.q. Hou 2020-02-24 5:50 ` Z.q. Hou 2020-02-13 4:06 ` [PATCHv10 09/13] PCI: mobiveil: Add Header Type field check Zhiqiang Hou 2020-02-13 4:06 ` Zhiqiang Hou 2020-02-20 17:31 ` Andrew Murray 2020-02-20 17:31 ` Andrew Murray 2020-02-24 5:50 ` Z.q. Hou 2020-02-24 5:50 ` Z.q. Hou 2020-02-13 4:06 ` [PATCHv10 10/13] dt-bindings: PCI: Add NXP Layerscape SoCs PCIe Gen4 controller Zhiqiang Hou 2020-02-13 4:06 ` Zhiqiang Hou 2020-02-13 4:06 ` [PATCHv10 11/13] PCI: mobiveil: Add PCIe Gen4 RC driver for NXP Layerscape SoCs Zhiqiang Hou 2020-02-13 4:06 ` Zhiqiang Hou 2020-02-20 17:43 ` Andrew Murray 2020-02-20 17:43 ` Andrew Murray 2020-02-24 5:50 ` Z.q. Hou 2020-02-24 5:50 ` Z.q. Hou 2020-02-21 12:17 ` Lorenzo Pieralisi 2020-02-21 12:17 ` Lorenzo Pieralisi 2020-02-24 5:58 ` Z.q. Hou 2020-02-24 5:58 ` Z.q. Hou 2020-02-13 4:06 ` [PATCHv10 12/13] arm64: dts: lx2160a: Add PCIe controller DT nodes Zhiqiang Hou 2020-02-13 4:06 ` Zhiqiang Hou 2020-02-24 1:28 ` Shawn Guo 2020-02-24 1:28 ` Shawn Guo 2020-02-24 6:11 ` Z.q. Hou 2020-02-24 6:11 ` Z.q. Hou 2020-02-13 4:06 ` [PATCHv10 13/13] arm64: defconfig: Enable CONFIG_PCIE_LAYERSCAPE_GEN4 Zhiqiang Hou 2020-02-13 4:06 ` Zhiqiang Hou 2020-02-24 1:29 ` Shawn Guo 2020-02-24 1:29 ` Shawn Guo 2020-02-21 12:19 ` [PATCHv10 00/13] PCI: Recode Mobiveil driver and add PCIe Gen4 driver for NXP Layerscape SoCs Lorenzo Pieralisi 2020-02-21 12:19 ` Lorenzo Pieralisi 2020-02-24 6:07 ` Z.q. Hou 2020-02-24 6:07 ` Z.q. Hou
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