From: Andre Przywara <andre.przywara@arm.com> To: Rob Herring <robh@kernel.org>, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: Robert Richter <rric@kernel.org>, soc@kernel.org, Jon Loeliger <jdl@jdl.com>, Mark Langsdorf <mlangsdo@redhat.com>, Eric Auger <eric.auger@redhat.com>, Will Deacon <will@kernel.org>, Catalin Marinas <catalin.marinas@arm.com> Subject: [PATCH 10/13] dt-bindings: memory-controllers: convert Calxeda DDR to json-schema Date: Wed, 26 Feb 2020 18:08:58 +0000 [thread overview] Message-ID: <20200226180901.89940-11-andre.przywara@arm.com> (raw) In-Reply-To: <20200226180901.89940-1-andre.przywara@arm.com> Convert the Calxeda DDR memory controller binding to DT schema format using json-schema. Although this technically covers the whole DRAM controller, the intention to use it only for error reporting and mapping fault addresses to DRAM chips. Signed-off-by: Andre Przywara <andre.przywara@arm.com> --- .../memory-controllers/calxeda-ddr-ctrlr.txt | 16 -------- .../memory-controllers/calxeda-ddr-ctrlr.yaml | 41 +++++++++++++++++++ 2 files changed, 41 insertions(+), 16 deletions(-) delete mode 100644 Documentation/devicetree/bindings/memory-controllers/calxeda-ddr-ctrlr.txt create mode 100644 Documentation/devicetree/bindings/memory-controllers/calxeda-ddr-ctrlr.yaml diff --git a/Documentation/devicetree/bindings/memory-controllers/calxeda-ddr-ctrlr.txt b/Documentation/devicetree/bindings/memory-controllers/calxeda-ddr-ctrlr.txt deleted file mode 100644 index 049675944b78..000000000000 --- a/Documentation/devicetree/bindings/memory-controllers/calxeda-ddr-ctrlr.txt +++ /dev/null @@ -1,16 +0,0 @@ -Calxeda DDR memory controller - -Properties: -- compatible : Should be: - - "calxeda,hb-ddr-ctrl" for ECX-1000 - - "calxeda,ecx-2000-ddr-ctrl" for ECX-2000 -- reg : Address and size for DDR controller registers. -- interrupts : Interrupt for DDR controller. - -Example: - - memory-controller@fff00000 { - compatible = "calxeda,hb-ddr-ctrl"; - reg = <0xfff00000 0x1000>; - interrupts = <0 91 4>; - }; diff --git a/Documentation/devicetree/bindings/memory-controllers/calxeda-ddr-ctrlr.yaml b/Documentation/devicetree/bindings/memory-controllers/calxeda-ddr-ctrlr.yaml new file mode 100644 index 000000000000..c5153127e722 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/calxeda-ddr-ctrlr.yaml @@ -0,0 +1,41 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/calxeda-ddr-ctrlr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Calxeda DDR memory controller binding + +description: | + The Calxeda DDR memory controller is initialised and programmed by the + firmware, but an OS might want to read its registers for error reporting + purposes and to learn about the DRAM topology. + +maintainers: + - Andre Przywara <andre.przywara@arm.com> + +properties: + compatible: + items: + - enum: + - calxeda,hb-ddr-ctrl + - calxeda,ecx-2000-ddr-ctrl + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +examples: + - | + memory-controller@fff00000 { + compatible = "calxeda,hb-ddr-ctrl"; + reg = <0xfff00000 0x1000>; + interrupts = <0 91 4>; + }; -- 2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: Andre Przywara <andre.przywara@arm.com> To: Rob Herring <robh@kernel.org>, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: Jon Loeliger <jdl@jdl.com>, Mark Langsdorf <mlangsdo@redhat.com>, Robert Richter <rric@kernel.org>, Catalin Marinas <catalin.marinas@arm.com>, Eric Auger <eric.auger@redhat.com>, soc@kernel.org, Will Deacon <will@kernel.org> Subject: [PATCH 10/13] dt-bindings: memory-controllers: convert Calxeda DDR to json-schema Date: Wed, 26 Feb 2020 18:08:58 +0000 [thread overview] Message-ID: <20200226180901.89940-11-andre.przywara@arm.com> (raw) In-Reply-To: <20200226180901.89940-1-andre.przywara@arm.com> Convert the Calxeda DDR memory controller binding to DT schema format using json-schema. Although this technically covers the whole DRAM controller, the intention to use it only for error reporting and mapping fault addresses to DRAM chips. Signed-off-by: Andre Przywara <andre.przywara@arm.com> --- .../memory-controllers/calxeda-ddr-ctrlr.txt | 16 -------- .../memory-controllers/calxeda-ddr-ctrlr.yaml | 41 +++++++++++++++++++ 2 files changed, 41 insertions(+), 16 deletions(-) delete mode 100644 Documentation/devicetree/bindings/memory-controllers/calxeda-ddr-ctrlr.txt create mode 100644 Documentation/devicetree/bindings/memory-controllers/calxeda-ddr-ctrlr.yaml diff --git a/Documentation/devicetree/bindings/memory-controllers/calxeda-ddr-ctrlr.txt b/Documentation/devicetree/bindings/memory-controllers/calxeda-ddr-ctrlr.txt deleted file mode 100644 index 049675944b78..000000000000 --- a/Documentation/devicetree/bindings/memory-controllers/calxeda-ddr-ctrlr.txt +++ /dev/null @@ -1,16 +0,0 @@ -Calxeda DDR memory controller - -Properties: -- compatible : Should be: - - "calxeda,hb-ddr-ctrl" for ECX-1000 - - "calxeda,ecx-2000-ddr-ctrl" for ECX-2000 -- reg : Address and size for DDR controller registers. -- interrupts : Interrupt for DDR controller. - -Example: - - memory-controller@fff00000 { - compatible = "calxeda,hb-ddr-ctrl"; - reg = <0xfff00000 0x1000>; - interrupts = <0 91 4>; - }; diff --git a/Documentation/devicetree/bindings/memory-controllers/calxeda-ddr-ctrlr.yaml b/Documentation/devicetree/bindings/memory-controllers/calxeda-ddr-ctrlr.yaml new file mode 100644 index 000000000000..c5153127e722 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/calxeda-ddr-ctrlr.yaml @@ -0,0 +1,41 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/calxeda-ddr-ctrlr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Calxeda DDR memory controller binding + +description: | + The Calxeda DDR memory controller is initialised and programmed by the + firmware, but an OS might want to read its registers for error reporting + purposes and to learn about the DRAM topology. + +maintainers: + - Andre Przywara <andre.przywara@arm.com> + +properties: + compatible: + items: + - enum: + - calxeda,hb-ddr-ctrl + - calxeda,ecx-2000-ddr-ctrl + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +examples: + - | + memory-controller@fff00000 { + compatible = "calxeda,hb-ddr-ctrl"; + reg = <0xfff00000 0x1000>; + interrupts = <0 91 4>; + }; -- 2.17.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-02-26 18:09 UTC|newest] Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-02-26 18:08 [PATCH 00/13] arm: calxeda: update DTS, bindings and MAINTAINERS Andre Przywara 2020-02-26 18:08 ` Andre Przywara 2020-02-26 18:08 ` [PATCH 01/13] arm: dts: calxeda: Basic DT file fixes Andre Przywara 2020-02-26 18:08 ` Andre Przywara 2020-02-26 18:08 ` [PATCH 02/13] arm: dts: calxeda: Provide UART clock Andre Przywara 2020-02-26 18:08 ` Andre Przywara 2020-02-26 18:08 ` [PATCH 03/13] arm: dts: calxeda: Fix interrupt grouping Andre Przywara 2020-02-26 18:08 ` Andre Przywara 2020-02-26 18:08 ` [PATCH 04/13] arm: dts: calxeda: Group port-phys and sgpio-gpio items Andre Przywara 2020-02-26 18:08 ` Andre Przywara 2020-02-26 18:08 ` [PATCH 05/13] dt-bindings: clock: Convert Calxeda clock bindings to json-schema Andre Przywara 2020-02-26 18:08 ` Andre Przywara 2020-02-26 18:24 ` Maxime Ripard 2020-02-26 18:24 ` Maxime Ripard 2020-02-26 18:08 ` [PATCH 06/13] dt-bindings: sata: Convert Calxeda SATA controller " Andre Przywara 2020-02-26 18:08 ` Andre Przywara 2020-02-26 18:25 ` Maxime Ripard 2020-02-26 18:25 ` Maxime Ripard 2020-02-26 18:08 ` [PATCH 07/13] dt-bindings: net: Convert Calxeda Ethernet binding " Andre Przywara 2020-02-26 18:08 ` Andre Przywara 2020-02-26 18:26 ` Maxime Ripard 2020-02-26 18:26 ` Maxime Ripard 2020-02-26 18:08 ` [PATCH 08/13] dt-bindings: phy: Convert Calxeda ComboPHY " Andre Przywara 2020-02-26 18:08 ` Andre Przywara 2020-02-26 18:26 ` Maxime Ripard 2020-02-26 18:26 ` Maxime Ripard 2020-02-26 18:08 ` [PATCH 09/13] dt-bindings: arm: Convert Calxeda L2 cache controller " Andre Przywara 2020-02-26 18:08 ` Andre Przywara 2020-02-26 18:08 ` Andre Przywara [this message] 2020-02-26 18:08 ` [PATCH 10/13] dt-bindings: memory-controllers: convert Calxeda DDR " Andre Przywara 2020-02-26 18:27 ` Maxime Ripard 2020-02-26 18:27 ` Maxime Ripard 2020-02-26 18:08 ` [PATCH 11/13] dt-bindings: ipmi: Convert IPMI-SMIC bindings " Andre Przywara 2020-02-26 18:08 ` Andre Przywara 2020-02-26 18:09 ` [PATCH 12/13] dt-bindings: arm: Add Calxeda system registers json-schema binding Andre Przywara 2020-02-26 18:09 ` Andre Przywara 2020-02-26 21:57 ` Rob Herring 2020-02-26 21:57 ` Rob Herring 2020-02-27 0:12 ` André Przywara 2020-02-27 0:12 ` André Przywara 2020-02-27 14:44 ` Rob Herring 2020-02-27 14:44 ` Rob Herring 2020-02-26 18:09 ` [PATCH 13/13] MAINTAINERS: Update Calxeda Highbank maintainership Andre Przywara 2020-02-26 18:09 ` Andre Przywara
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