From: Francisco Jerez <currojerez@riseup.net> To: linux-pm@vger.kernel.org, intel-gfx@lists.freedesktop.org Cc: "Rafael J. Wysocki" <rjw@rjwysocki.net>, "Pandruvada, Srinivas" <srinivas.pandruvada@intel.com>, "Vivi, Rodrigo" <rodrigo.vivi@intel.com>, Peter Zijlstra <peterz@infradead.org>, Fengguang Wu <fengguang.wu@intel.com>, Julia Lawall <julia.lawall@lip6.fr> Subject: [PATCH 10/10] OPTIONAL: cpufreq: intel_pstate: Expose VLP controller parameters via debugfs. Date: Tue, 10 Mar 2020 14:42:03 -0700 [thread overview] Message-ID: <20200310214203.26459-11-currojerez@riseup.net> (raw) In-Reply-To: <20200310214203.26459-1-currojerez@riseup.net> This is not required for the controller to work but has proven very useful for debugging and testing of alternative heuristic parameters, which may offer a better trade-off between energy efficiency and latency. A warning is printed out which should taint the kernel for the non-standard calibration of the heuristic to be obvious in bug reports. v2: Use DEFINE_DEBUGFS_ATTRIBUTE rather than DEFINE_SIMPLE_ATTRIBUTE for debugfs files (Julia). Add realtime statistic threshold and averaging frequency parameters. Signed-off-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Fengguang Wu <fengguang.wu@intel.com> Signed-off-by: Julia Lawall <julia.lawall@lip6.fr> --- drivers/cpufreq/intel_pstate.c | 92 ++++++++++++++++++++++++++++++++++ 1 file changed, 92 insertions(+) diff --git a/drivers/cpufreq/intel_pstate.c b/drivers/cpufreq/intel_pstate.c index c4558a131660..ab893a211746 100644 --- a/drivers/cpufreq/intel_pstate.c +++ b/drivers/cpufreq/intel_pstate.c @@ -1030,6 +1030,94 @@ static void intel_pstate_update_limits(unsigned int cpu) mutex_unlock(&intel_pstate_driver_lock); } +/************************** debugfs begin ************************/ +static void intel_pstate_reset_vlp(struct cpudata *cpu); + +static int vlp_param_set(void *data, u64 val) +{ + unsigned int cpu; + + *(u32 *)data = val; + for_each_possible_cpu(cpu) { + if (all_cpu_data[cpu]) + intel_pstate_reset_vlp(all_cpu_data[cpu]); + } + + WARN_ONCE(1, "Unsupported P-state VLP parameter update via debugging interface"); + + return 0; +} + +static int vlp_param_get(void *data, u64 *val) +{ + *val = *(u32 *)data; + return 0; +} +DEFINE_DEBUGFS_ATTRIBUTE(fops_vlp_param, vlp_param_get, vlp_param_set, + "%llu\n"); + +static struct dentry *debugfs_parent; + +struct vlp_param { + char *name; + void *value; + struct dentry *dentry; +}; + +static struct vlp_param vlp_files[] = { + {"vlp_sample_interval_ms", &vlp_params.sample_interval_ms, }, + {"vlp_setpoint_0_pml", &vlp_params.setpoint_0_pml, }, + {"vlp_setpoint_aggr_pml", &vlp_params.setpoint_aggr_pml, }, + {"vlp_avg_hz", &vlp_params.avg_hz, }, + {"vlp_realtime_gain_pml", &vlp_params.realtime_gain_pml, }, + {"vlp_debug", &vlp_params.debug, }, + {NULL, NULL, } +}; + +static void intel_pstate_update_util_hwp_vlp(struct update_util_data *data, + u64 time, unsigned int flags); + +static void intel_pstate_debug_expose_params(void) +{ + int i; + + if (pstate_funcs.update_util != intel_pstate_update_util_hwp_vlp) + return; + + debugfs_parent = debugfs_create_dir("pstate_snb", NULL); + if (IS_ERR_OR_NULL(debugfs_parent)) + return; + + for (i = 0; vlp_files[i].name; i++) { + struct dentry *dentry; + + dentry = debugfs_create_file_unsafe(vlp_files[i].name, 0660, + debugfs_parent, + vlp_files[i].value, + &fops_vlp_param); + if (!IS_ERR(dentry)) + vlp_files[i].dentry = dentry; + } +} + +static void intel_pstate_debug_hide_params(void) +{ + int i; + + if (IS_ERR_OR_NULL(debugfs_parent)) + return; + + for (i = 0; vlp_files[i].name; i++) { + debugfs_remove(vlp_files[i].dentry); + vlp_files[i].dentry = NULL; + } + + debugfs_remove(debugfs_parent); + debugfs_parent = NULL; +} + +/************************** debugfs end ************************/ + /************************** sysfs begin ************************/ #define show_one(file_name, object) \ static ssize_t show_##file_name \ @@ -2970,6 +3058,8 @@ static int intel_pstate_register_driver(struct cpufreq_driver *driver) global.min_perf_pct = min_perf_pct_min(); + intel_pstate_debug_expose_params(); + return 0; } @@ -2978,6 +3068,8 @@ static int intel_pstate_unregister_driver(void) if (hwp_active) return -EBUSY; + intel_pstate_debug_hide_params(); + cpufreq_unregister_driver(intel_pstate_driver); intel_pstate_driver_cleanup(); -- 2.22.1
WARNING: multiple messages have this Message-ID (diff)
From: Francisco Jerez <currojerez@riseup.net> To: linux-pm@vger.kernel.org, intel-gfx@lists.freedesktop.org Cc: Peter Zijlstra <peterz@infradead.org>, "Rafael J. Wysocki" <rjw@rjwysocki.net>, Julia Lawall <julia.lawall@lip6.fr>, "Pandruvada, Srinivas" <srinivas.pandruvada@intel.com>, Fengguang Wu <fengguang.wu@intel.com> Subject: [Intel-gfx] [PATCH 10/10] OPTIONAL: cpufreq: intel_pstate: Expose VLP controller parameters via debugfs. Date: Tue, 10 Mar 2020 14:42:03 -0700 [thread overview] Message-ID: <20200310214203.26459-11-currojerez@riseup.net> (raw) In-Reply-To: <20200310214203.26459-1-currojerez@riseup.net> This is not required for the controller to work but has proven very useful for debugging and testing of alternative heuristic parameters, which may offer a better trade-off between energy efficiency and latency. A warning is printed out which should taint the kernel for the non-standard calibration of the heuristic to be obvious in bug reports. v2: Use DEFINE_DEBUGFS_ATTRIBUTE rather than DEFINE_SIMPLE_ATTRIBUTE for debugfs files (Julia). Add realtime statistic threshold and averaging frequency parameters. Signed-off-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Fengguang Wu <fengguang.wu@intel.com> Signed-off-by: Julia Lawall <julia.lawall@lip6.fr> --- drivers/cpufreq/intel_pstate.c | 92 ++++++++++++++++++++++++++++++++++ 1 file changed, 92 insertions(+) diff --git a/drivers/cpufreq/intel_pstate.c b/drivers/cpufreq/intel_pstate.c index c4558a131660..ab893a211746 100644 --- a/drivers/cpufreq/intel_pstate.c +++ b/drivers/cpufreq/intel_pstate.c @@ -1030,6 +1030,94 @@ static void intel_pstate_update_limits(unsigned int cpu) mutex_unlock(&intel_pstate_driver_lock); } +/************************** debugfs begin ************************/ +static void intel_pstate_reset_vlp(struct cpudata *cpu); + +static int vlp_param_set(void *data, u64 val) +{ + unsigned int cpu; + + *(u32 *)data = val; + for_each_possible_cpu(cpu) { + if (all_cpu_data[cpu]) + intel_pstate_reset_vlp(all_cpu_data[cpu]); + } + + WARN_ONCE(1, "Unsupported P-state VLP parameter update via debugging interface"); + + return 0; +} + +static int vlp_param_get(void *data, u64 *val) +{ + *val = *(u32 *)data; + return 0; +} +DEFINE_DEBUGFS_ATTRIBUTE(fops_vlp_param, vlp_param_get, vlp_param_set, + "%llu\n"); + +static struct dentry *debugfs_parent; + +struct vlp_param { + char *name; + void *value; + struct dentry *dentry; +}; + +static struct vlp_param vlp_files[] = { + {"vlp_sample_interval_ms", &vlp_params.sample_interval_ms, }, + {"vlp_setpoint_0_pml", &vlp_params.setpoint_0_pml, }, + {"vlp_setpoint_aggr_pml", &vlp_params.setpoint_aggr_pml, }, + {"vlp_avg_hz", &vlp_params.avg_hz, }, + {"vlp_realtime_gain_pml", &vlp_params.realtime_gain_pml, }, + {"vlp_debug", &vlp_params.debug, }, + {NULL, NULL, } +}; + +static void intel_pstate_update_util_hwp_vlp(struct update_util_data *data, + u64 time, unsigned int flags); + +static void intel_pstate_debug_expose_params(void) +{ + int i; + + if (pstate_funcs.update_util != intel_pstate_update_util_hwp_vlp) + return; + + debugfs_parent = debugfs_create_dir("pstate_snb", NULL); + if (IS_ERR_OR_NULL(debugfs_parent)) + return; + + for (i = 0; vlp_files[i].name; i++) { + struct dentry *dentry; + + dentry = debugfs_create_file_unsafe(vlp_files[i].name, 0660, + debugfs_parent, + vlp_files[i].value, + &fops_vlp_param); + if (!IS_ERR(dentry)) + vlp_files[i].dentry = dentry; + } +} + +static void intel_pstate_debug_hide_params(void) +{ + int i; + + if (IS_ERR_OR_NULL(debugfs_parent)) + return; + + for (i = 0; vlp_files[i].name; i++) { + debugfs_remove(vlp_files[i].dentry); + vlp_files[i].dentry = NULL; + } + + debugfs_remove(debugfs_parent); + debugfs_parent = NULL; +} + +/************************** debugfs end ************************/ + /************************** sysfs begin ************************/ #define show_one(file_name, object) \ static ssize_t show_##file_name \ @@ -2970,6 +3058,8 @@ static int intel_pstate_register_driver(struct cpufreq_driver *driver) global.min_perf_pct = min_perf_pct_min(); + intel_pstate_debug_expose_params(); + return 0; } @@ -2978,6 +3068,8 @@ static int intel_pstate_unregister_driver(void) if (hwp_active) return -EBUSY; + intel_pstate_debug_hide_params(); + cpufreq_unregister_driver(intel_pstate_driver); intel_pstate_driver_cleanup(); -- 2.22.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2020-03-10 21:46 UTC|newest] Thread overview: 85+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-03-10 21:41 [RFC] GPU-bound energy efficiency improvements for the intel_pstate driver (v2) Francisco Jerez 2020-03-10 21:41 ` [Intel-gfx] " Francisco Jerez 2020-03-10 21:41 ` [PATCH 01/10] PM: QoS: Add CPU_RESPONSE_FREQUENCY global PM QoS limit Francisco Jerez 2020-03-10 21:41 ` [Intel-gfx] " Francisco Jerez 2020-03-11 12:42 ` Peter Zijlstra 2020-03-11 12:42 ` [Intel-gfx] " Peter Zijlstra 2020-03-11 19:23 ` Francisco Jerez 2020-03-11 19:23 ` [Intel-gfx] " Francisco Jerez 2020-03-11 19:23 ` [PATCHv2 " Francisco Jerez 2020-03-11 19:23 ` [Intel-gfx] " Francisco Jerez 2020-03-19 10:25 ` Rafael J. Wysocki 2020-03-19 10:25 ` [Intel-gfx] " Rafael J. Wysocki 2020-03-10 21:41 ` [PATCH 02/10] drm/i915: Adjust PM QoS response frequency based on GPU load Francisco Jerez 2020-03-10 21:41 ` [Intel-gfx] " Francisco Jerez 2020-03-10 22:26 ` Chris Wilson 2020-03-10 22:26 ` Chris Wilson 2020-03-11 0:34 ` Francisco Jerez 2020-03-11 0:34 ` Francisco Jerez 2020-03-18 19:42 ` Francisco Jerez 2020-03-18 19:42 ` Francisco Jerez 2020-03-20 2:46 ` Francisco Jerez 2020-03-20 2:46 ` Francisco Jerez 2020-03-20 10:06 ` Chris Wilson 2020-03-20 10:06 ` Chris Wilson 2020-03-11 10:00 ` Tvrtko Ursulin 2020-03-11 10:00 ` Tvrtko Ursulin 2020-03-11 10:21 ` Chris Wilson 2020-03-11 10:21 ` Chris Wilson 2020-03-11 19:54 ` Francisco Jerez 2020-03-11 19:54 ` Francisco Jerez 2020-03-12 11:52 ` Tvrtko Ursulin 2020-03-12 11:52 ` Tvrtko Ursulin 2020-03-13 7:39 ` Francisco Jerez 2020-03-13 7:39 ` Francisco Jerez 2020-03-16 20:54 ` Francisco Jerez 2020-03-16 20:54 ` Francisco Jerez 2020-03-10 21:41 ` [PATCH 03/10] OPTIONAL: drm/i915: Expose PM QoS control parameters via debugfs Francisco Jerez 2020-03-10 21:41 ` [Intel-gfx] " Francisco Jerez 2020-03-10 21:41 ` [PATCH 04/10] Revert "cpufreq: intel_pstate: Drop ->update_util from pstate_funcs" Francisco Jerez 2020-03-10 21:41 ` [Intel-gfx] " Francisco Jerez 2020-03-19 10:45 ` Rafael J. Wysocki 2020-03-19 10:45 ` [Intel-gfx] " Rafael J. Wysocki 2020-03-10 21:41 ` [PATCH 05/10] cpufreq: intel_pstate: Implement VLP controller statistics and status calculation Francisco Jerez 2020-03-10 21:41 ` [Intel-gfx] " Francisco Jerez 2020-03-19 11:06 ` Rafael J. Wysocki 2020-03-19 11:06 ` [Intel-gfx] " Rafael J. Wysocki 2020-03-10 21:41 ` [PATCH 06/10] cpufreq: intel_pstate: Implement VLP controller target P-state range estimation Francisco Jerez 2020-03-10 21:41 ` [Intel-gfx] " Francisco Jerez 2020-03-19 11:12 ` Rafael J. Wysocki 2020-03-19 11:12 ` [Intel-gfx] " Rafael J. Wysocki 2020-03-10 21:42 ` [PATCH 07/10] cpufreq: intel_pstate: Implement VLP controller for HWP parts Francisco Jerez 2020-03-10 21:42 ` [Intel-gfx] " Francisco Jerez 2020-03-17 23:59 ` Pandruvada, Srinivas 2020-03-17 23:59 ` [Intel-gfx] " Pandruvada, Srinivas 2020-03-18 19:51 ` Francisco Jerez 2020-03-18 19:51 ` [Intel-gfx] " Francisco Jerez 2020-03-18 20:10 ` Pandruvada, Srinivas 2020-03-18 20:10 ` [Intel-gfx] " Pandruvada, Srinivas 2020-03-18 20:22 ` Francisco Jerez 2020-03-18 20:22 ` [Intel-gfx] " Francisco Jerez 2020-03-23 20:13 ` Pandruvada, Srinivas 2020-03-23 20:13 ` [Intel-gfx] " Pandruvada, Srinivas 2020-03-10 21:42 ` [PATCH 08/10] cpufreq: intel_pstate: Enable VLP controller based on ACPI FADT profile and CPUID Francisco Jerez 2020-03-10 21:42 ` [Intel-gfx] " Francisco Jerez 2020-03-19 11:20 ` Rafael J. Wysocki 2020-03-19 11:20 ` [Intel-gfx] " Rafael J. Wysocki 2020-03-10 21:42 ` [PATCH 09/10] OPTIONAL: cpufreq: intel_pstate: Add tracing of VLP controller status Francisco Jerez 2020-03-10 21:42 ` [Intel-gfx] " Francisco Jerez 2020-03-10 21:42 ` Francisco Jerez [this message] 2020-03-10 21:42 ` [Intel-gfx] [PATCH 10/10] OPTIONAL: cpufreq: intel_pstate: Expose VLP controller parameters via debugfs Francisco Jerez 2020-03-11 2:35 ` [RFC] GPU-bound energy efficiency improvements for the intel_pstate driver (v2) Pandruvada, Srinivas 2020-03-11 2:35 ` [Intel-gfx] " Pandruvada, Srinivas 2020-03-11 3:55 ` Francisco Jerez 2020-03-11 3:55 ` [Intel-gfx] " Francisco Jerez 2020-03-11 4:25 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for " Patchwork 2020-03-12 2:31 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for GPU-bound energy efficiency improvements for the intel_pstate driver (v2). (rev2) Patchwork 2020-03-12 2:32 ` Patchwork 2020-03-23 23:29 ` [RFC] GPU-bound energy efficiency improvements for the intel_pstate driver (v2) Pandruvada, Srinivas 2020-03-23 23:29 ` [Intel-gfx] " Pandruvada, Srinivas 2020-03-24 0:23 ` Francisco Jerez 2020-03-24 0:23 ` [Intel-gfx] " Francisco Jerez 2020-03-24 19:16 ` Francisco Jerez 2020-03-24 19:16 ` [Intel-gfx] " Francisco Jerez 2020-03-24 20:03 ` Pandruvada, Srinivas 2020-03-24 20:03 ` [Intel-gfx] " Pandruvada, Srinivas
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