From: Francisco Jerez <currojerez@riseup.net> To: linux-pm@vger.kernel.org, intel-gfx@lists.freedesktop.org Cc: "Rafael J. Wysocki" <rjw@rjwysocki.net>, "Pandruvada, Srinivas" <srinivas.pandruvada@intel.com>, "Vivi, Rodrigo" <rodrigo.vivi@intel.com>, Peter Zijlstra <peterz@infradead.org> Subject: [PATCH 03/10] OPTIONAL: drm/i915: Expose PM QoS control parameters via debugfs. Date: Tue, 10 Mar 2020 14:41:56 -0700 [thread overview] Message-ID: <20200310214203.26459-4-currojerez@riseup.net> (raw) In-Reply-To: <20200310214203.26459-1-currojerez@riseup.net> Signed-off-by: Francisco Jerez <currojerez@riseup.net> --- drivers/gpu/drm/i915/i915_debugfs.c | 69 +++++++++++++++++++++++++++++ 1 file changed, 69 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 8f2525e4ce0f..e5c27b9302d9 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -1745,6 +1745,72 @@ static const struct file_operations i915_guc_log_relay_fops = { .release = i915_guc_log_relay_release, }; +static int +i915_rf_qos_delay_max_ns_set(void *data, u64 val) +{ + struct drm_i915_private *dev_priv = data; + + WRITE_ONCE(dev_priv->gt.rf_qos.delay_max_ns, val); + return 0; +} + +static int +i915_rf_qos_delay_max_ns_get(void *data, u64 *val) +{ + struct drm_i915_private *dev_priv = data; + + *val = READ_ONCE(dev_priv->gt.rf_qos.delay_max_ns); + return 0; +} + +DEFINE_SIMPLE_ATTRIBUTE(i915_rf_qos_delay_max_ns_fops, + i915_rf_qos_delay_max_ns_get, + i915_rf_qos_delay_max_ns_set, "%llu\n"); + +static int +i915_rf_qos_delay_slope_shift_set(void *data, u64 val) +{ + struct drm_i915_private *dev_priv = data; + + WRITE_ONCE(dev_priv->gt.rf_qos.delay_slope_shift, val); + return 0; +} + +static int +i915_rf_qos_delay_slope_shift_get(void *data, u64 *val) +{ + struct drm_i915_private *dev_priv = data; + + *val = READ_ONCE(dev_priv->gt.rf_qos.delay_slope_shift); + return 0; +} + +DEFINE_SIMPLE_ATTRIBUTE(i915_rf_qos_delay_slope_shift_fops, + i915_rf_qos_delay_slope_shift_get, + i915_rf_qos_delay_slope_shift_set, "%llu\n"); + +static int +i915_rf_qos_target_hz_set(void *data, u64 val) +{ + struct drm_i915_private *dev_priv = data; + + WRITE_ONCE(dev_priv->gt.rf_qos.target_hz, val); + return 0; +} + +static int +i915_rf_qos_target_hz_get(void *data, u64 *val) +{ + struct drm_i915_private *dev_priv = data; + + *val = READ_ONCE(dev_priv->gt.rf_qos.target_hz); + return 0; +} + +DEFINE_SIMPLE_ATTRIBUTE(i915_rf_qos_target_hz_fops, + i915_rf_qos_target_hz_get, + i915_rf_qos_target_hz_set, "%llu\n"); + static int i915_runtime_pm_status(struct seq_file *m, void *unused) { struct drm_i915_private *dev_priv = node_to_i915(m->private); @@ -2390,6 +2456,9 @@ static const struct i915_debugfs_files { #endif {"i915_guc_log_level", &i915_guc_log_level_fops}, {"i915_guc_log_relay", &i915_guc_log_relay_fops}, + {"i915_rf_qos_delay_max_ns", &i915_rf_qos_delay_max_ns_fops}, + {"i915_rf_qos_delay_slope_shift", &i915_rf_qos_delay_slope_shift_fops}, + {"i915_rf_qos_target_hz", &i915_rf_qos_target_hz_fops} }; int i915_debugfs_register(struct drm_i915_private *dev_priv) -- 2.22.1
WARNING: multiple messages have this Message-ID (diff)
From: Francisco Jerez <currojerez@riseup.net> To: linux-pm@vger.kernel.org, intel-gfx@lists.freedesktop.org Cc: Peter Zijlstra <peterz@infradead.org>, "Rafael J. Wysocki" <rjw@rjwysocki.net>, "Pandruvada, Srinivas" <srinivas.pandruvada@intel.com> Subject: [Intel-gfx] [PATCH 03/10] OPTIONAL: drm/i915: Expose PM QoS control parameters via debugfs. Date: Tue, 10 Mar 2020 14:41:56 -0700 [thread overview] Message-ID: <20200310214203.26459-4-currojerez@riseup.net> (raw) In-Reply-To: <20200310214203.26459-1-currojerez@riseup.net> Signed-off-by: Francisco Jerez <currojerez@riseup.net> --- drivers/gpu/drm/i915/i915_debugfs.c | 69 +++++++++++++++++++++++++++++ 1 file changed, 69 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 8f2525e4ce0f..e5c27b9302d9 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -1745,6 +1745,72 @@ static const struct file_operations i915_guc_log_relay_fops = { .release = i915_guc_log_relay_release, }; +static int +i915_rf_qos_delay_max_ns_set(void *data, u64 val) +{ + struct drm_i915_private *dev_priv = data; + + WRITE_ONCE(dev_priv->gt.rf_qos.delay_max_ns, val); + return 0; +} + +static int +i915_rf_qos_delay_max_ns_get(void *data, u64 *val) +{ + struct drm_i915_private *dev_priv = data; + + *val = READ_ONCE(dev_priv->gt.rf_qos.delay_max_ns); + return 0; +} + +DEFINE_SIMPLE_ATTRIBUTE(i915_rf_qos_delay_max_ns_fops, + i915_rf_qos_delay_max_ns_get, + i915_rf_qos_delay_max_ns_set, "%llu\n"); + +static int +i915_rf_qos_delay_slope_shift_set(void *data, u64 val) +{ + struct drm_i915_private *dev_priv = data; + + WRITE_ONCE(dev_priv->gt.rf_qos.delay_slope_shift, val); + return 0; +} + +static int +i915_rf_qos_delay_slope_shift_get(void *data, u64 *val) +{ + struct drm_i915_private *dev_priv = data; + + *val = READ_ONCE(dev_priv->gt.rf_qos.delay_slope_shift); + return 0; +} + +DEFINE_SIMPLE_ATTRIBUTE(i915_rf_qos_delay_slope_shift_fops, + i915_rf_qos_delay_slope_shift_get, + i915_rf_qos_delay_slope_shift_set, "%llu\n"); + +static int +i915_rf_qos_target_hz_set(void *data, u64 val) +{ + struct drm_i915_private *dev_priv = data; + + WRITE_ONCE(dev_priv->gt.rf_qos.target_hz, val); + return 0; +} + +static int +i915_rf_qos_target_hz_get(void *data, u64 *val) +{ + struct drm_i915_private *dev_priv = data; + + *val = READ_ONCE(dev_priv->gt.rf_qos.target_hz); + return 0; +} + +DEFINE_SIMPLE_ATTRIBUTE(i915_rf_qos_target_hz_fops, + i915_rf_qos_target_hz_get, + i915_rf_qos_target_hz_set, "%llu\n"); + static int i915_runtime_pm_status(struct seq_file *m, void *unused) { struct drm_i915_private *dev_priv = node_to_i915(m->private); @@ -2390,6 +2456,9 @@ static const struct i915_debugfs_files { #endif {"i915_guc_log_level", &i915_guc_log_level_fops}, {"i915_guc_log_relay", &i915_guc_log_relay_fops}, + {"i915_rf_qos_delay_max_ns", &i915_rf_qos_delay_max_ns_fops}, + {"i915_rf_qos_delay_slope_shift", &i915_rf_qos_delay_slope_shift_fops}, + {"i915_rf_qos_target_hz", &i915_rf_qos_target_hz_fops} }; int i915_debugfs_register(struct drm_i915_private *dev_priv) -- 2.22.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2020-03-10 21:46 UTC|newest] Thread overview: 85+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-03-10 21:41 [RFC] GPU-bound energy efficiency improvements for the intel_pstate driver (v2) Francisco Jerez 2020-03-10 21:41 ` [Intel-gfx] " Francisco Jerez 2020-03-10 21:41 ` [PATCH 01/10] PM: QoS: Add CPU_RESPONSE_FREQUENCY global PM QoS limit Francisco Jerez 2020-03-10 21:41 ` [Intel-gfx] " Francisco Jerez 2020-03-11 12:42 ` Peter Zijlstra 2020-03-11 12:42 ` [Intel-gfx] " Peter Zijlstra 2020-03-11 19:23 ` Francisco Jerez 2020-03-11 19:23 ` [Intel-gfx] " Francisco Jerez 2020-03-11 19:23 ` [PATCHv2 " Francisco Jerez 2020-03-11 19:23 ` [Intel-gfx] " Francisco Jerez 2020-03-19 10:25 ` Rafael J. Wysocki 2020-03-19 10:25 ` [Intel-gfx] " Rafael J. Wysocki 2020-03-10 21:41 ` [PATCH 02/10] drm/i915: Adjust PM QoS response frequency based on GPU load Francisco Jerez 2020-03-10 21:41 ` [Intel-gfx] " Francisco Jerez 2020-03-10 22:26 ` Chris Wilson 2020-03-10 22:26 ` Chris Wilson 2020-03-11 0:34 ` Francisco Jerez 2020-03-11 0:34 ` Francisco Jerez 2020-03-18 19:42 ` Francisco Jerez 2020-03-18 19:42 ` Francisco Jerez 2020-03-20 2:46 ` Francisco Jerez 2020-03-20 2:46 ` Francisco Jerez 2020-03-20 10:06 ` Chris Wilson 2020-03-20 10:06 ` Chris Wilson 2020-03-11 10:00 ` Tvrtko Ursulin 2020-03-11 10:00 ` Tvrtko Ursulin 2020-03-11 10:21 ` Chris Wilson 2020-03-11 10:21 ` Chris Wilson 2020-03-11 19:54 ` Francisco Jerez 2020-03-11 19:54 ` Francisco Jerez 2020-03-12 11:52 ` Tvrtko Ursulin 2020-03-12 11:52 ` Tvrtko Ursulin 2020-03-13 7:39 ` Francisco Jerez 2020-03-13 7:39 ` Francisco Jerez 2020-03-16 20:54 ` Francisco Jerez 2020-03-16 20:54 ` Francisco Jerez 2020-03-10 21:41 ` Francisco Jerez [this message] 2020-03-10 21:41 ` [Intel-gfx] [PATCH 03/10] OPTIONAL: drm/i915: Expose PM QoS control parameters via debugfs Francisco Jerez 2020-03-10 21:41 ` [PATCH 04/10] Revert "cpufreq: intel_pstate: Drop ->update_util from pstate_funcs" Francisco Jerez 2020-03-10 21:41 ` [Intel-gfx] " Francisco Jerez 2020-03-19 10:45 ` Rafael J. Wysocki 2020-03-19 10:45 ` [Intel-gfx] " Rafael J. Wysocki 2020-03-10 21:41 ` [PATCH 05/10] cpufreq: intel_pstate: Implement VLP controller statistics and status calculation Francisco Jerez 2020-03-10 21:41 ` [Intel-gfx] " Francisco Jerez 2020-03-19 11:06 ` Rafael J. Wysocki 2020-03-19 11:06 ` [Intel-gfx] " Rafael J. Wysocki 2020-03-10 21:41 ` [PATCH 06/10] cpufreq: intel_pstate: Implement VLP controller target P-state range estimation Francisco Jerez 2020-03-10 21:41 ` [Intel-gfx] " Francisco Jerez 2020-03-19 11:12 ` Rafael J. Wysocki 2020-03-19 11:12 ` [Intel-gfx] " Rafael J. Wysocki 2020-03-10 21:42 ` [PATCH 07/10] cpufreq: intel_pstate: Implement VLP controller for HWP parts Francisco Jerez 2020-03-10 21:42 ` [Intel-gfx] " Francisco Jerez 2020-03-17 23:59 ` Pandruvada, Srinivas 2020-03-17 23:59 ` [Intel-gfx] " Pandruvada, Srinivas 2020-03-18 19:51 ` Francisco Jerez 2020-03-18 19:51 ` [Intel-gfx] " Francisco Jerez 2020-03-18 20:10 ` Pandruvada, Srinivas 2020-03-18 20:10 ` [Intel-gfx] " Pandruvada, Srinivas 2020-03-18 20:22 ` Francisco Jerez 2020-03-18 20:22 ` [Intel-gfx] " Francisco Jerez 2020-03-23 20:13 ` Pandruvada, Srinivas 2020-03-23 20:13 ` [Intel-gfx] " Pandruvada, Srinivas 2020-03-10 21:42 ` [PATCH 08/10] cpufreq: intel_pstate: Enable VLP controller based on ACPI FADT profile and CPUID Francisco Jerez 2020-03-10 21:42 ` [Intel-gfx] " Francisco Jerez 2020-03-19 11:20 ` Rafael J. Wysocki 2020-03-19 11:20 ` [Intel-gfx] " Rafael J. Wysocki 2020-03-10 21:42 ` [PATCH 09/10] OPTIONAL: cpufreq: intel_pstate: Add tracing of VLP controller status Francisco Jerez 2020-03-10 21:42 ` [Intel-gfx] " Francisco Jerez 2020-03-10 21:42 ` [PATCH 10/10] OPTIONAL: cpufreq: intel_pstate: Expose VLP controller parameters via debugfs Francisco Jerez 2020-03-10 21:42 ` [Intel-gfx] " Francisco Jerez 2020-03-11 2:35 ` [RFC] GPU-bound energy efficiency improvements for the intel_pstate driver (v2) Pandruvada, Srinivas 2020-03-11 2:35 ` [Intel-gfx] " Pandruvada, Srinivas 2020-03-11 3:55 ` Francisco Jerez 2020-03-11 3:55 ` [Intel-gfx] " Francisco Jerez 2020-03-11 4:25 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for " Patchwork 2020-03-12 2:31 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for GPU-bound energy efficiency improvements for the intel_pstate driver (v2). (rev2) Patchwork 2020-03-12 2:32 ` Patchwork 2020-03-23 23:29 ` [RFC] GPU-bound energy efficiency improvements for the intel_pstate driver (v2) Pandruvada, Srinivas 2020-03-23 23:29 ` [Intel-gfx] " Pandruvada, Srinivas 2020-03-24 0:23 ` Francisco Jerez 2020-03-24 0:23 ` [Intel-gfx] " Francisco Jerez 2020-03-24 19:16 ` Francisco Jerez 2020-03-24 19:16 ` [Intel-gfx] " Francisco Jerez 2020-03-24 20:03 ` Pandruvada, Srinivas 2020-03-24 20:03 ` [Intel-gfx] " Pandruvada, Srinivas
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