From: Jitao Shi <jitao.shi@mediatek.com>
To: Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Matthias Brugger <matthias.bgg@gmail.com>,
Daniel Vetter <daniel@ffwll.ch>, David Airlie <airlied@linux.ie>,
<dri-devel@lists.freedesktop.org>, <linux-kernel@vger.kernel.org>
Cc: <linux-mediatek@lists.infradead.org>,
<devicetree@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<srv_heupstream@mediatek.com>, <yingjoe.chen@mediatek.com>,
<eddie.huang@mediatek.com>, <cawa.cheng@mediatek.com>,
<bibby.hsieh@mediatek.com>, <ck.hu@mediatek.com>,
<stonea168@163.com>, <huijuan.xie@mediatek.com>,
Jitao Shi <jitao.shi@mediatek.com>
Subject: [PATCH v3 4/4] drm/mediatek: config mipitx impedance with calibration data
Date: Wed, 11 Mar 2020 15:40:32 +0800 [thread overview]
Message-ID: <20200311074032.119481-5-jitao.shi@mediatek.com> (raw)
In-Reply-To: <20200311074032.119481-1-jitao.shi@mediatek.com>
Read calibration data from nvmem, and config mipitx impedance with
calibration data to make sure their impedance are 100ohm.
Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c | 57 +++++++++++++++++++
1 file changed, 57 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c b/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c
index 124fdf95f1e5..878feeb7ac6c 100644
--- a/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c
+++ b/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c
@@ -5,6 +5,8 @@
*/
#include "mtk_mipi_tx.h"
+#include <linux/nvmem-consumer.h>
+#include <linux/slab.h>
#define MIPITX_LANE_CON 0x000c
#define RG_DSI_CPHY_T1DRV_EN BIT(0)
@@ -28,6 +30,7 @@
#define MIPITX_PLL_CON4 0x003c
#define RG_DSI_PLL_IBIAS (3 << 10)
+#define MIPITX_D2P_RTCODE 0x0100
#define MIPITX_D2_SW_CTL_EN 0x0144
#define MIPITX_D0_SW_CTL_EN 0x0244
#define MIPITX_CK_CKMODE_EN 0x0328
@@ -108,6 +111,58 @@ static const struct clk_ops mtk_mipi_tx_pll_ops = {
.recalc_rate = mtk_mipi_tx_pll_recalc_rate,
};
+static void mtk_mipi_tx_config_calibration_data(struct mtk_mipi_tx *mipi_tx)
+{
+ u32 *buf;
+ u32 rt_code[5];
+ int i, j;
+ struct nvmem_cell *cell;
+ struct device *dev = mipi_tx->dev;
+ size_t len;
+
+ cell = nvmem_cell_get(dev, "calibration-data");
+ if (IS_ERR(cell)) {
+ dev_info(dev, "nvmem_cell_get fail\n");
+ return;
+ }
+
+ buf = (u32 *)nvmem_cell_read(cell, &len);
+
+ nvmem_cell_put(cell);
+
+ if (IS_ERR(buf)) {
+ dev_info(dev, "can't get data\n");
+ return;
+ }
+
+ if (len < 3 * sizeof(u32)) {
+ dev_info(dev, "invalid calibration data\n");
+ kfree(buf);
+ return;
+ }
+
+ rt_code[0] = ((buf[0] >> 6 & 0x1f) << 5) | (buf[0] >> 11 & 0x1f);
+ rt_code[1] = ((buf[1] >> 27 & 0x1f) << 5) | (buf[0] >> 1 & 0x1f);
+ rt_code[2] = ((buf[1] >> 17 & 0x1f) << 5) | (buf[1] >> 22 & 0x1f);
+ rt_code[3] = ((buf[1] >> 7 & 0x1f) << 5) | (buf[1] >> 12 & 0x1f);
+ rt_code[4] = ((buf[2] >> 27 & 0x1f) << 5) | (buf[1] >> 2 & 0x1f);
+
+ for (i = 0; i < 5; i++) {
+ if ((rt_code[i] & 0x1f) == 0)
+ rt_code[i] |= 0x10;
+
+ if ((rt_code[i] >> 5 & 0x1f) == 0)
+ rt_code[i] |= 0x10 << 5;
+
+ for (j = 0; j < 10; j++)
+ mtk_mipi_tx_update_bits(mipi_tx,
+ MIPITX_D2P_RTCODE * (i + 1) + j * 4,
+ 1, rt_code[i] >> j & 1);
+ }
+
+ kfree(buf);
+}
+
static void mtk_mipi_tx_power_on_signal(struct phy *phy)
{
struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy);
@@ -130,6 +185,8 @@ static void mtk_mipi_tx_power_on_signal(struct phy *phy)
RG_DSI_HSTX_LDO_REF_SEL,
mipi_tx->mipitx_drive << 6);
+ mtk_mipi_tx_config_calibration_data(mipi_tx);
+
mtk_mipi_tx_set_bits(mipi_tx, MIPITX_CK_CKMODE_EN, DSI_CK_CKMODE_EN);
}
--
2.21.0
WARNING: multiple messages have this Message-ID (diff)
From: Jitao Shi <jitao.shi@mediatek.com>
To: Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Matthias Brugger <matthias.bgg@gmail.com>,
Daniel Vetter <daniel@ffwll.ch>, David Airlie <airlied@linux.ie>,
<dri-devel@lists.freedesktop.org>, <linux-kernel@vger.kernel.org>
Cc: devicetree@vger.kernel.org, Jitao Shi <jitao.shi@mediatek.com>,
srv_heupstream@mediatek.com, huijuan.xie@mediatek.com,
stonea168@163.com, cawa.cheng@mediatek.com,
linux-mediatek@lists.infradead.org, bibby.hsieh@mediatek.com,
ck.hu@mediatek.com, yingjoe.chen@mediatek.com,
eddie.huang@mediatek.com, linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 4/4] drm/mediatek: config mipitx impedance with calibration data
Date: Wed, 11 Mar 2020 15:40:32 +0800 [thread overview]
Message-ID: <20200311074032.119481-5-jitao.shi@mediatek.com> (raw)
In-Reply-To: <20200311074032.119481-1-jitao.shi@mediatek.com>
Read calibration data from nvmem, and config mipitx impedance with
calibration data to make sure their impedance are 100ohm.
Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c | 57 +++++++++++++++++++
1 file changed, 57 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c b/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c
index 124fdf95f1e5..878feeb7ac6c 100644
--- a/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c
+++ b/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c
@@ -5,6 +5,8 @@
*/
#include "mtk_mipi_tx.h"
+#include <linux/nvmem-consumer.h>
+#include <linux/slab.h>
#define MIPITX_LANE_CON 0x000c
#define RG_DSI_CPHY_T1DRV_EN BIT(0)
@@ -28,6 +30,7 @@
#define MIPITX_PLL_CON4 0x003c
#define RG_DSI_PLL_IBIAS (3 << 10)
+#define MIPITX_D2P_RTCODE 0x0100
#define MIPITX_D2_SW_CTL_EN 0x0144
#define MIPITX_D0_SW_CTL_EN 0x0244
#define MIPITX_CK_CKMODE_EN 0x0328
@@ -108,6 +111,58 @@ static const struct clk_ops mtk_mipi_tx_pll_ops = {
.recalc_rate = mtk_mipi_tx_pll_recalc_rate,
};
+static void mtk_mipi_tx_config_calibration_data(struct mtk_mipi_tx *mipi_tx)
+{
+ u32 *buf;
+ u32 rt_code[5];
+ int i, j;
+ struct nvmem_cell *cell;
+ struct device *dev = mipi_tx->dev;
+ size_t len;
+
+ cell = nvmem_cell_get(dev, "calibration-data");
+ if (IS_ERR(cell)) {
+ dev_info(dev, "nvmem_cell_get fail\n");
+ return;
+ }
+
+ buf = (u32 *)nvmem_cell_read(cell, &len);
+
+ nvmem_cell_put(cell);
+
+ if (IS_ERR(buf)) {
+ dev_info(dev, "can't get data\n");
+ return;
+ }
+
+ if (len < 3 * sizeof(u32)) {
+ dev_info(dev, "invalid calibration data\n");
+ kfree(buf);
+ return;
+ }
+
+ rt_code[0] = ((buf[0] >> 6 & 0x1f) << 5) | (buf[0] >> 11 & 0x1f);
+ rt_code[1] = ((buf[1] >> 27 & 0x1f) << 5) | (buf[0] >> 1 & 0x1f);
+ rt_code[2] = ((buf[1] >> 17 & 0x1f) << 5) | (buf[1] >> 22 & 0x1f);
+ rt_code[3] = ((buf[1] >> 7 & 0x1f) << 5) | (buf[1] >> 12 & 0x1f);
+ rt_code[4] = ((buf[2] >> 27 & 0x1f) << 5) | (buf[1] >> 2 & 0x1f);
+
+ for (i = 0; i < 5; i++) {
+ if ((rt_code[i] & 0x1f) == 0)
+ rt_code[i] |= 0x10;
+
+ if ((rt_code[i] >> 5 & 0x1f) == 0)
+ rt_code[i] |= 0x10 << 5;
+
+ for (j = 0; j < 10; j++)
+ mtk_mipi_tx_update_bits(mipi_tx,
+ MIPITX_D2P_RTCODE * (i + 1) + j * 4,
+ 1, rt_code[i] >> j & 1);
+ }
+
+ kfree(buf);
+}
+
static void mtk_mipi_tx_power_on_signal(struct phy *phy)
{
struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy);
@@ -130,6 +185,8 @@ static void mtk_mipi_tx_power_on_signal(struct phy *phy)
RG_DSI_HSTX_LDO_REF_SEL,
mipi_tx->mipitx_drive << 6);
+ mtk_mipi_tx_config_calibration_data(mipi_tx);
+
mtk_mipi_tx_set_bits(mipi_tx, MIPITX_CK_CKMODE_EN, DSI_CK_CKMODE_EN);
}
--
2.21.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
WARNING: multiple messages have this Message-ID (diff)
From: Jitao Shi <jitao.shi@mediatek.com>
To: Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Matthias Brugger <matthias.bgg@gmail.com>,
Daniel Vetter <daniel@ffwll.ch>, David Airlie <airlied@linux.ie>,
<dri-devel@lists.freedesktop.org>, <linux-kernel@vger.kernel.org>
Cc: devicetree@vger.kernel.org, Jitao Shi <jitao.shi@mediatek.com>,
srv_heupstream@mediatek.com, huijuan.xie@mediatek.com,
stonea168@163.com, cawa.cheng@mediatek.com,
linux-mediatek@lists.infradead.org, bibby.hsieh@mediatek.com,
ck.hu@mediatek.com, yingjoe.chen@mediatek.com,
eddie.huang@mediatek.com, linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 4/4] drm/mediatek: config mipitx impedance with calibration data
Date: Wed, 11 Mar 2020 15:40:32 +0800 [thread overview]
Message-ID: <20200311074032.119481-5-jitao.shi@mediatek.com> (raw)
In-Reply-To: <20200311074032.119481-1-jitao.shi@mediatek.com>
Read calibration data from nvmem, and config mipitx impedance with
calibration data to make sure their impedance are 100ohm.
Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c | 57 +++++++++++++++++++
1 file changed, 57 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c b/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c
index 124fdf95f1e5..878feeb7ac6c 100644
--- a/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c
+++ b/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c
@@ -5,6 +5,8 @@
*/
#include "mtk_mipi_tx.h"
+#include <linux/nvmem-consumer.h>
+#include <linux/slab.h>
#define MIPITX_LANE_CON 0x000c
#define RG_DSI_CPHY_T1DRV_EN BIT(0)
@@ -28,6 +30,7 @@
#define MIPITX_PLL_CON4 0x003c
#define RG_DSI_PLL_IBIAS (3 << 10)
+#define MIPITX_D2P_RTCODE 0x0100
#define MIPITX_D2_SW_CTL_EN 0x0144
#define MIPITX_D0_SW_CTL_EN 0x0244
#define MIPITX_CK_CKMODE_EN 0x0328
@@ -108,6 +111,58 @@ static const struct clk_ops mtk_mipi_tx_pll_ops = {
.recalc_rate = mtk_mipi_tx_pll_recalc_rate,
};
+static void mtk_mipi_tx_config_calibration_data(struct mtk_mipi_tx *mipi_tx)
+{
+ u32 *buf;
+ u32 rt_code[5];
+ int i, j;
+ struct nvmem_cell *cell;
+ struct device *dev = mipi_tx->dev;
+ size_t len;
+
+ cell = nvmem_cell_get(dev, "calibration-data");
+ if (IS_ERR(cell)) {
+ dev_info(dev, "nvmem_cell_get fail\n");
+ return;
+ }
+
+ buf = (u32 *)nvmem_cell_read(cell, &len);
+
+ nvmem_cell_put(cell);
+
+ if (IS_ERR(buf)) {
+ dev_info(dev, "can't get data\n");
+ return;
+ }
+
+ if (len < 3 * sizeof(u32)) {
+ dev_info(dev, "invalid calibration data\n");
+ kfree(buf);
+ return;
+ }
+
+ rt_code[0] = ((buf[0] >> 6 & 0x1f) << 5) | (buf[0] >> 11 & 0x1f);
+ rt_code[1] = ((buf[1] >> 27 & 0x1f) << 5) | (buf[0] >> 1 & 0x1f);
+ rt_code[2] = ((buf[1] >> 17 & 0x1f) << 5) | (buf[1] >> 22 & 0x1f);
+ rt_code[3] = ((buf[1] >> 7 & 0x1f) << 5) | (buf[1] >> 12 & 0x1f);
+ rt_code[4] = ((buf[2] >> 27 & 0x1f) << 5) | (buf[1] >> 2 & 0x1f);
+
+ for (i = 0; i < 5; i++) {
+ if ((rt_code[i] & 0x1f) == 0)
+ rt_code[i] |= 0x10;
+
+ if ((rt_code[i] >> 5 & 0x1f) == 0)
+ rt_code[i] |= 0x10 << 5;
+
+ for (j = 0; j < 10; j++)
+ mtk_mipi_tx_update_bits(mipi_tx,
+ MIPITX_D2P_RTCODE * (i + 1) + j * 4,
+ 1, rt_code[i] >> j & 1);
+ }
+
+ kfree(buf);
+}
+
static void mtk_mipi_tx_power_on_signal(struct phy *phy)
{
struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy);
@@ -130,6 +185,8 @@ static void mtk_mipi_tx_power_on_signal(struct phy *phy)
RG_DSI_HSTX_LDO_REF_SEL,
mipi_tx->mipitx_drive << 6);
+ mtk_mipi_tx_config_calibration_data(mipi_tx);
+
mtk_mipi_tx_set_bits(mipi_tx, MIPITX_CK_CKMODE_EN, DSI_CK_CKMODE_EN);
}
--
2.21.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
WARNING: multiple messages have this Message-ID (diff)
From: Jitao Shi <jitao.shi@mediatek.com>
To: Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Matthias Brugger <matthias.bgg@gmail.com>,
Daniel Vetter <daniel@ffwll.ch>, David Airlie <airlied@linux.ie>,
<dri-devel@lists.freedesktop.org>, <linux-kernel@vger.kernel.org>
Cc: devicetree@vger.kernel.org, Jitao Shi <jitao.shi@mediatek.com>,
srv_heupstream@mediatek.com, huijuan.xie@mediatek.com,
stonea168@163.com, cawa.cheng@mediatek.com,
linux-mediatek@lists.infradead.org, yingjoe.chen@mediatek.com,
eddie.huang@mediatek.com, linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 4/4] drm/mediatek: config mipitx impedance with calibration data
Date: Wed, 11 Mar 2020 15:40:32 +0800 [thread overview]
Message-ID: <20200311074032.119481-5-jitao.shi@mediatek.com> (raw)
In-Reply-To: <20200311074032.119481-1-jitao.shi@mediatek.com>
Read calibration data from nvmem, and config mipitx impedance with
calibration data to make sure their impedance are 100ohm.
Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c | 57 +++++++++++++++++++
1 file changed, 57 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c b/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c
index 124fdf95f1e5..878feeb7ac6c 100644
--- a/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c
+++ b/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c
@@ -5,6 +5,8 @@
*/
#include "mtk_mipi_tx.h"
+#include <linux/nvmem-consumer.h>
+#include <linux/slab.h>
#define MIPITX_LANE_CON 0x000c
#define RG_DSI_CPHY_T1DRV_EN BIT(0)
@@ -28,6 +30,7 @@
#define MIPITX_PLL_CON4 0x003c
#define RG_DSI_PLL_IBIAS (3 << 10)
+#define MIPITX_D2P_RTCODE 0x0100
#define MIPITX_D2_SW_CTL_EN 0x0144
#define MIPITX_D0_SW_CTL_EN 0x0244
#define MIPITX_CK_CKMODE_EN 0x0328
@@ -108,6 +111,58 @@ static const struct clk_ops mtk_mipi_tx_pll_ops = {
.recalc_rate = mtk_mipi_tx_pll_recalc_rate,
};
+static void mtk_mipi_tx_config_calibration_data(struct mtk_mipi_tx *mipi_tx)
+{
+ u32 *buf;
+ u32 rt_code[5];
+ int i, j;
+ struct nvmem_cell *cell;
+ struct device *dev = mipi_tx->dev;
+ size_t len;
+
+ cell = nvmem_cell_get(dev, "calibration-data");
+ if (IS_ERR(cell)) {
+ dev_info(dev, "nvmem_cell_get fail\n");
+ return;
+ }
+
+ buf = (u32 *)nvmem_cell_read(cell, &len);
+
+ nvmem_cell_put(cell);
+
+ if (IS_ERR(buf)) {
+ dev_info(dev, "can't get data\n");
+ return;
+ }
+
+ if (len < 3 * sizeof(u32)) {
+ dev_info(dev, "invalid calibration data\n");
+ kfree(buf);
+ return;
+ }
+
+ rt_code[0] = ((buf[0] >> 6 & 0x1f) << 5) | (buf[0] >> 11 & 0x1f);
+ rt_code[1] = ((buf[1] >> 27 & 0x1f) << 5) | (buf[0] >> 1 & 0x1f);
+ rt_code[2] = ((buf[1] >> 17 & 0x1f) << 5) | (buf[1] >> 22 & 0x1f);
+ rt_code[3] = ((buf[1] >> 7 & 0x1f) << 5) | (buf[1] >> 12 & 0x1f);
+ rt_code[4] = ((buf[2] >> 27 & 0x1f) << 5) | (buf[1] >> 2 & 0x1f);
+
+ for (i = 0; i < 5; i++) {
+ if ((rt_code[i] & 0x1f) == 0)
+ rt_code[i] |= 0x10;
+
+ if ((rt_code[i] >> 5 & 0x1f) == 0)
+ rt_code[i] |= 0x10 << 5;
+
+ for (j = 0; j < 10; j++)
+ mtk_mipi_tx_update_bits(mipi_tx,
+ MIPITX_D2P_RTCODE * (i + 1) + j * 4,
+ 1, rt_code[i] >> j & 1);
+ }
+
+ kfree(buf);
+}
+
static void mtk_mipi_tx_power_on_signal(struct phy *phy)
{
struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy);
@@ -130,6 +185,8 @@ static void mtk_mipi_tx_power_on_signal(struct phy *phy)
RG_DSI_HSTX_LDO_REF_SEL,
mipi_tx->mipitx_drive << 6);
+ mtk_mipi_tx_config_calibration_data(mipi_tx);
+
mtk_mipi_tx_set_bits(mipi_tx, MIPITX_CK_CKMODE_EN, DSI_CK_CKMODE_EN);
}
--
2.21.0
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
next prev parent reply other threads:[~2020-03-11 7:41 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-11 7:40 [PATCH v3 0/4] Config mipi tx drive current and impedance Jitao Shi
2020-03-11 7:40 ` Jitao Shi
2020-03-11 7:40 ` Jitao Shi
2020-03-11 7:40 ` Jitao Shi
2020-03-11 7:40 ` [PATCH v3 1/4] dt-bindings: display: mediatek: add property to control mipi tx drive current Jitao Shi
2020-03-11 7:40 ` Jitao Shi
2020-03-11 7:40 ` Jitao Shi
2020-03-11 7:40 ` Jitao Shi
2020-03-23 22:00 ` Rob Herring
2020-03-23 22:00 ` Rob Herring
2020-03-23 22:00 ` Rob Herring
2020-03-23 22:00 ` Rob Herring
2020-03-31 7:09 ` Jitao Shi
2020-03-31 7:09 ` Jitao Shi
2020-03-31 7:09 ` Jitao Shi
2020-03-31 7:09 ` Jitao Shi
2020-03-11 7:40 ` [PATCH v3 2/4] dt-bindings: display: mediatek: get mipitx calibration data from nvmem Jitao Shi
2020-03-11 7:40 ` Jitao Shi
2020-03-11 7:40 ` Jitao Shi
2020-03-11 7:40 ` Jitao Shi
2020-03-23 22:01 ` Rob Herring
2020-03-23 22:01 ` Rob Herring
2020-03-23 22:01 ` Rob Herring
2020-03-23 22:01 ` Rob Herring
2020-03-11 7:40 ` [PATCH v3 3/4] drm/mediatek: add the mipitx driving control Jitao Shi
2020-03-11 7:40 ` Jitao Shi
2020-03-11 7:40 ` Jitao Shi
2020-03-11 7:40 ` Jitao Shi
2020-03-11 7:40 ` Jitao Shi [this message]
2020-03-11 7:40 ` [PATCH v3 4/4] drm/mediatek: config mipitx impedance with calibration data Jitao Shi
2020-03-11 7:40 ` Jitao Shi
2020-03-11 7:40 ` Jitao Shi
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