[PATCH v2 0/3] More improvements for multiple PLICs

From: Anup Patel <anup.patel@wdc.com>
To: Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Thomas Gleixner <tglx@linutronix.de>,
	Jason Cooper <jason@lakedaemon.net>,
	Marc Zyngier <maz@kernel.org>
Cc: Atish Patra <atish.patra@wdc.com>,
	Alistair Francis <Alistair.Francis@wdc.com>,
	Anup Patel <anup@brainfault.org>,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	Anup Patel <anup.patel@wdc.com>
Subject: [PATCH v2 0/3] More improvements for multiple PLICs
Date: Mon, 18 May 2020 14:44:38 +0530	[thread overview]
Message-ID: <20200518091441.94843-1-anup.patel@wdc.com> (raw)

This series does more improvements for supporting multiple PLIC
instances.

PATCH1 and PATCH2 are fixes whereas PATCH3 helps users distinguish
multiple PLIC instances in boot prints.

These patches are based up Linux-5.7-rc5 and can be found at
plic_imp_v2 branch at: https://github.com/avpatel/linux.git

To try this patches, we will need:
1. OpenSBI multi-PLIC and multi-CLINT support which can be found in
   multi_plic_clint_v1 branch at:
   https://github.com/avpatel/opensbi.git
2. QEMU RISC-V multi-socket support which can be found in
   riscv_multi_socket_v1 branch at:
   https://github.com/avpatel/qemu.git

Changes since v1:
 - Re-arranged PATCHs to have fixes first
 - Added Fixes tag to PATCH1 and PATCH2
 - Use %pOFP in boot print to distinguish PLIC instance

Anup Patel (3):
  irqchip/sifive-plic: Set default irq affinity in plic_irqdomain_map()
  irqchip/sifive-plic: Setup cpuhp once after boot CPU handler is
    present
  irqchip/sifive-plic: Improve boot prints for multiple PLIC instances

 drivers/irqchip/irq-sifive-plic.c | 21 +++++++++++++++++----
 1 file changed, 17 insertions(+), 4 deletions(-)

-- 
2.25.1