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From: Palmer Dabbelt <palmer@dabbelt.com>
To: Anup Patel <Anup.Patel@wdc.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
	tglx@linutronix.de, jason@lakedaemon.net,
	Marc Zyngier <maz@kernel.org>, Atish Patra <Atish.Patra@wdc.com>,
	Alistair Francis <Alistair.Francis@wdc.com>,
	anup@brainfault.org, linux-riscv@lists.infradead.org,
	linux-kernel@vger.kernel.org, Anup Patel <Anup.Patel@wdc.com>
Subject: Re: [PATCH v2 0/3] More improvements for multiple PLICs
Date: Thu, 21 May 2020 15:06:21 -0700 (PDT)	[thread overview]
Message-ID: <mhng-a2588163-0a87-494f-af68-59f0ca15965c@palmerdabbelt-glaptop1> (raw)
In-Reply-To: <20200518091441.94843-1-anup.patel@wdc.com>

On Mon, 18 May 2020 02:14:38 PDT (-0700), Anup Patel wrote:
> This series does more improvements for supporting multiple PLIC
> instances.
>
> PATCH1 and PATCH2 are fixes whereas PATCH3 helps users distinguish
> multiple PLIC instances in boot prints.
>
> These patches are based up Linux-5.7-rc5 and can be found at
> plic_imp_v2 branch at: https://github.com/avpatel/linux.git
>
> To try this patches, we will need:
> 1. OpenSBI multi-PLIC and multi-CLINT support which can be found in
>    multi_plic_clint_v1 branch at:
>    https://github.com/avpatel/opensbi.git
> 2. QEMU RISC-V multi-socket support which can be found in
>    riscv_multi_socket_v1 branch at:
>    https://github.com/avpatel/qemu.git
>
> Changes since v1:
>  - Re-arranged PATCHs to have fixes first
>  - Added Fixes tag to PATCH1 and PATCH2
>  - Use %pOFP in boot print to distinguish PLIC instance
>
> Anup Patel (3):
>   irqchip/sifive-plic: Set default irq affinity in plic_irqdomain_map()
>   irqchip/sifive-plic: Setup cpuhp once after boot CPU handler is
>     present
>   irqchip/sifive-plic: Improve boot prints for multiple PLIC instances
>
>  drivers/irqchip/irq-sifive-plic.c | 21 +++++++++++++++++----
>  1 file changed, 17 insertions(+), 4 deletions(-)

Thanks!  Aside from that parallelism question this LGTM.  IIRC Marc picked up
the last round, so I'm assuming this would go in through his tree as well.

WARNING: multiple messages have this Message-ID (diff)
From: Palmer Dabbelt <palmer@dabbelt.com>
To: Anup Patel <Anup.Patel@wdc.com>
Cc: jason@lakedaemon.net, Marc Zyngier <maz@kernel.org>,
	anup@brainfault.org, Anup Patel <Anup.Patel@wdc.com>,
	linux-kernel@vger.kernel.org, Atish Patra <Atish.Patra@wdc.com>,
	Alistair Francis <Alistair.Francis@wdc.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	tglx@linutronix.de, linux-riscv@lists.infradead.org
Subject: Re: [PATCH v2 0/3] More improvements for multiple PLICs
Date: Thu, 21 May 2020 15:06:21 -0700 (PDT)	[thread overview]
Message-ID: <mhng-a2588163-0a87-494f-af68-59f0ca15965c@palmerdabbelt-glaptop1> (raw)
In-Reply-To: <20200518091441.94843-1-anup.patel@wdc.com>

On Mon, 18 May 2020 02:14:38 PDT (-0700), Anup Patel wrote:
> This series does more improvements for supporting multiple PLIC
> instances.
>
> PATCH1 and PATCH2 are fixes whereas PATCH3 helps users distinguish
> multiple PLIC instances in boot prints.
>
> These patches are based up Linux-5.7-rc5 and can be found at
> plic_imp_v2 branch at: https://github.com/avpatel/linux.git
>
> To try this patches, we will need:
> 1. OpenSBI multi-PLIC and multi-CLINT support which can be found in
>    multi_plic_clint_v1 branch at:
>    https://github.com/avpatel/opensbi.git
> 2. QEMU RISC-V multi-socket support which can be found in
>    riscv_multi_socket_v1 branch at:
>    https://github.com/avpatel/qemu.git
>
> Changes since v1:
>  - Re-arranged PATCHs to have fixes first
>  - Added Fixes tag to PATCH1 and PATCH2
>  - Use %pOFP in boot print to distinguish PLIC instance
>
> Anup Patel (3):
>   irqchip/sifive-plic: Set default irq affinity in plic_irqdomain_map()
>   irqchip/sifive-plic: Setup cpuhp once after boot CPU handler is
>     present
>   irqchip/sifive-plic: Improve boot prints for multiple PLIC instances
>
>  drivers/irqchip/irq-sifive-plic.c | 21 +++++++++++++++++----
>  1 file changed, 17 insertions(+), 4 deletions(-)

Thanks!  Aside from that parallelism question this LGTM.  IIRC Marc picked up
the last round, so I'm assuming this would go in through his tree as well.


  parent reply	other threads:[~2020-05-21 22:06 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-18  9:14 [PATCH v2 0/3] More improvements for multiple PLICs Anup Patel
2020-05-18  9:14 ` Anup Patel
2020-05-18  9:14 ` [PATCH v2 1/3] irqchip/sifive-plic: Set default irq affinity in plic_irqdomain_map() Anup Patel
2020-05-18  9:14   ` Anup Patel
2020-05-21 22:06   ` Palmer Dabbelt
2020-05-21 22:06     ` Palmer Dabbelt
2020-05-22  6:44     ` Anup Patel
2020-05-22  6:44       ` Anup Patel
2020-05-30  7:46   ` [tip: irq/core] " tip-bot2 for Anup Patel
2020-05-18  9:14 ` [PATCH v2 2/3] irqchip/sifive-plic: Setup cpuhp once after boot CPU handler is present Anup Patel
2020-05-18  9:14   ` Anup Patel
2020-05-21 22:06   ` Palmer Dabbelt
2020-05-21 22:06     ` Palmer Dabbelt
2020-05-22  6:46     ` Anup Patel
2020-05-22  6:46       ` Anup Patel
2020-05-30  7:46   ` [tip: irq/core] " tip-bot2 for Anup Patel
2020-05-18  9:14 ` [PATCH v2 3/3] irqchip/sifive-plic: Improve boot prints for multiple PLIC instances Anup Patel
2020-05-18  9:14   ` Anup Patel
2020-05-21 22:06   ` Palmer Dabbelt
2020-05-21 22:06     ` Palmer Dabbelt
2020-05-30  7:46   ` [tip: irq/core] " tip-bot2 for Anup Patel
2020-05-21 22:06 ` Palmer Dabbelt [this message]
2020-05-21 22:06   ` [PATCH v2 0/3] More improvements for multiple PLICs Palmer Dabbelt
2020-05-25 10:08 ` Marc Zyngier
2020-05-25 10:08   ` Marc Zyngier

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