From: Catalin Marinas <catalin.marinas@arm.com>
To: Zhenyu Ye <yezhenyu2@huawei.com>
Cc: peterz@infradead.org, mark.rutland@arm.com, will@kernel.org,
aneesh.kumar@linux.ibm.com, akpm@linux-foundation.org,
npiggin@gmail.com, arnd@arndb.de, rostedt@goodmis.org,
maz@kernel.org, suzuki.poulose@arm.com, tglx@linutronix.de,
yuzhao@google.com, Dave.Martin@arm.com, steven.price@arm.com,
broonie@kernel.org, guohanjun@huawei.com,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org,
linux-mm@kvack.org, arm@kernel.org, xiexiangyou@huawei.com,
prime.zeng@hisilicon.com, zhangshaokun@hisilicon.com,
kuhn.chenqun@huawei.com
Subject: Re: [PATCH v2 1/6] arm64: Detect the ARMv8.4 TTL feature
Date: Fri, 22 May 2020 16:50:02 +0100 [thread overview]
Message-ID: <20200522155002.GF26492@gaia> (raw)
In-Reply-To: <20200423135656.2712-2-yezhenyu2@huawei.com>
On Thu, Apr 23, 2020 at 09:56:51PM +0800, Zhenyu Ye wrote:
> From: Marc Zyngier <maz@kernel.org>
>
> In order to reduce the cost of TLB invalidation, the ARMv8.4 TTL
> feature allows TLBs to be issued with a level allowing for quicker
> invalidation.
>
> The TTL field indicates the level of page table walk
> holding the leaf entry for the address being invalidated.
>
> Let's detect the feature for now. Further patches will implement
> its actual usage.
>
> Signed-off-by: Marc Zyngier <maz@kernel.org>
> Signed-off-by: Zhenyu Ye <yezhenyu2@huawei.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
WARNING: multiple messages have this Message-ID (diff)
From: Catalin Marinas <catalin.marinas@arm.com>
To: Zhenyu Ye <yezhenyu2@huawei.com>
Cc: mark.rutland@arm.com, peterz@infradead.org, linux-mm@kvack.org,
guohanjun@huawei.com, will@kernel.org,
linux-arch@vger.kernel.org, yuzhao@google.com,
aneesh.kumar@linux.ibm.com, steven.price@arm.com, arm@kernel.org,
Dave.Martin@arm.com, arnd@arndb.de, suzuki.poulose@arm.com,
npiggin@gmail.com, zhangshaokun@hisilicon.com,
broonie@kernel.org, rostedt@goodmis.org,
prime.zeng@hisilicon.com, kuhn.chenqun@huawei.com,
tglx@linutronix.de, linux-arm-kernel@lists.infradead.org,
xiexiangyou@huawei.com, linux-kernel@vger.kernel.org,
maz@kernel.org, akpm@linux-foundation.org
Subject: Re: [PATCH v2 1/6] arm64: Detect the ARMv8.4 TTL feature
Date: Fri, 22 May 2020 16:50:02 +0100 [thread overview]
Message-ID: <20200522155002.GF26492@gaia> (raw)
In-Reply-To: <20200423135656.2712-2-yezhenyu2@huawei.com>
On Thu, Apr 23, 2020 at 09:56:51PM +0800, Zhenyu Ye wrote:
> From: Marc Zyngier <maz@kernel.org>
>
> In order to reduce the cost of TLB invalidation, the ARMv8.4 TTL
> feature allows TLBs to be issued with a level allowing for quicker
> invalidation.
>
> The TTL field indicates the level of page table walk
> holding the leaf entry for the address being invalidated.
>
> Let's detect the feature for now. Further patches will implement
> its actual usage.
>
> Signed-off-by: Marc Zyngier <maz@kernel.org>
> Signed-off-by: Zhenyu Ye <yezhenyu2@huawei.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
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linux-arm-kernel mailing list
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next prev parent reply other threads:[~2020-05-22 15:50 UTC|newest]
Thread overview: 55+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-23 13:56 [PATCH v2 0/6] arm64: tlb: add support for TTL feature Zhenyu Ye
2020-04-23 13:56 ` Zhenyu Ye
2020-04-23 13:56 ` Zhenyu Ye
2020-04-23 13:56 ` [PATCH v2 1/6] arm64: Detect the ARMv8.4 " Zhenyu Ye
2020-04-23 13:56 ` Zhenyu Ye
2020-04-23 13:56 ` Zhenyu Ye
2020-05-22 15:50 ` Catalin Marinas [this message]
2020-05-22 15:50 ` Catalin Marinas
2020-04-23 13:56 ` [PATCH v2 2/6] arm64: Add level-hinted TLB invalidation helper Zhenyu Ye
2020-04-23 13:56 ` Zhenyu Ye
2020-04-23 13:56 ` Zhenyu Ye
2020-05-22 15:50 ` Catalin Marinas
2020-05-22 15:50 ` Catalin Marinas
2020-05-25 6:54 ` Zhenyu Ye
2020-05-25 6:54 ` Zhenyu Ye
2020-05-25 6:54 ` Zhenyu Ye
2020-04-23 13:56 ` [PATCH v2 3/6] arm64: Add tlbi_user_level " Zhenyu Ye
2020-04-23 13:56 ` Zhenyu Ye
2020-04-23 13:56 ` Zhenyu Ye
2020-05-22 15:49 ` Catalin Marinas
2020-05-22 15:49 ` Catalin Marinas
2020-05-25 6:57 ` Zhenyu Ye
2020-05-25 6:57 ` Zhenyu Ye
2020-05-25 6:57 ` Zhenyu Ye
2020-04-23 13:56 ` [PATCH v2 4/6] tlb: mmu_gather: add tlb_flush_*_range APIs Zhenyu Ye
2020-04-23 13:56 ` Zhenyu Ye
2020-04-23 13:56 ` Zhenyu Ye
2020-05-22 15:50 ` Catalin Marinas
2020-05-22 15:50 ` Catalin Marinas
2020-04-23 13:56 ` [PATCH v2 5/6] mm: tlb: Provide flush_*_tlb_range wrappers Zhenyu Ye
2020-04-23 13:56 ` Zhenyu Ye
2020-04-23 13:56 ` Zhenyu Ye
2020-05-22 15:42 ` Catalin Marinas
2020-05-22 15:42 ` Catalin Marinas
2020-05-25 7:19 ` Zhenyu Ye
2020-05-25 7:19 ` Zhenyu Ye
2020-05-25 7:19 ` Zhenyu Ye
2020-05-26 14:52 ` Catalin Marinas
2020-05-26 14:52 ` Catalin Marinas
2020-05-30 10:24 ` Zhenyu Ye
2020-05-30 10:24 ` Zhenyu Ye
2020-05-30 10:24 ` Zhenyu Ye
2020-06-01 11:56 ` Catalin Marinas
2020-06-01 11:56 ` Catalin Marinas
2020-06-01 13:36 ` Zhenyu Ye
2020-06-01 13:36 ` Zhenyu Ye
2020-06-01 13:36 ` Zhenyu Ye
2020-04-23 13:56 ` [PATCH v2 6/6] arm64: tlb: Set the TTL field in flush_tlb_range Zhenyu Ye
2020-04-23 13:56 ` Zhenyu Ye
2020-04-23 13:56 ` Zhenyu Ye
2020-05-26 14:56 ` Catalin Marinas
2020-05-26 14:56 ` Catalin Marinas
2020-05-11 12:41 ` [PATCH v2 0/6] arm64: tlb: add support for TTL feature Zhenyu Ye
2020-05-11 12:41 ` Zhenyu Ye
2020-05-11 12:41 ` Zhenyu Ye
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