From: Catalin Marinas <catalin.marinas@arm.com> To: Zhenyu Ye <yezhenyu2@huawei.com> Cc: peterz@infradead.org, mark.rutland@arm.com, will@kernel.org, aneesh.kumar@linux.ibm.com, akpm@linux-foundation.org, npiggin@gmail.com, arnd@arndb.de, rostedt@goodmis.org, maz@kernel.org, suzuki.poulose@arm.com, tglx@linutronix.de, yuzhao@google.com, Dave.Martin@arm.com, steven.price@arm.com, broonie@kernel.org, guohanjun@huawei.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org, linux-mm@kvack.org, arm@kernel.org, xiexiangyou@huawei.com, prime.zeng@hisilicon.com, zhangshaokun@hisilicon.com, kuhn.chenqun@huawei.com Subject: Re: [PATCH v2 5/6] mm: tlb: Provide flush_*_tlb_range wrappers Date: Mon, 1 Jun 2020 12:56:45 +0100 [thread overview] Message-ID: <20200601115644.GA23419@gaia> (raw) In-Reply-To: <0c6f79e4-f29a-d373-2e43-c4f87cf78b49@huawei.com> Hi Zhenyu, On Sat, May 30, 2020 at 06:24:21PM +0800, Zhenyu Ye wrote: > On 2020/5/26 22:52, Catalin Marinas wrote: > > On Mon, May 25, 2020 at 03:19:42PM +0800, Zhenyu Ye wrote: > >> tlb_flush_##_pxx##_range() is used to set tlb->cleared_*, > >> flush_##_pxx##_tlb_range() will actually flush the TLB entry. > >> > >> In arch64, tlb_flush_p?d_range() is defined as: > >> > >> #define flush_pmd_tlb_range(vma, addr, end) flush_tlb_range(vma, addr, end) > >> #define flush_pud_tlb_range(vma, addr, end) flush_tlb_range(vma, addr, end) > > > > Currently, flush_p??_tlb_range() are generic and defined as above. I > > think in the generic code they can remain an alias for > > flush_tlb_range(). > > > > On arm64, we can redefine them as: > > > > #define flush_pte_tlb_range(vma, addr, end) __flush_tlb_range(vma, addr, end, 3) > > #define flush_pmd_tlb_range(vma, addr, end) __flush_tlb_range(vma, addr, end, 2) > > #define flush_pud_tlb_range(vma, addr, end) __flush_tlb_range(vma, addr, end, 1) > > #define flush_p4d_tlb_range(vma, addr, end) __flush_tlb_range(vma, addr, end, 0) > > > > (unless the compiler optimises away all the mmu_gather stuff in your > > macro above but they don't look trivial to me) > > I changed generic code before considering that other structures may also > use this feature, such as Power9. And Peter may want to replace all > flush_tlb_range() by tlb_flush() in the future, see [1] for details. > > If only enable this feature on aarch64, your codes are better. > > [1] https://lore.kernel.org/linux-arm-kernel/20200402163849.GM20713@hirez.programming.kicks-ass.net/ But we change the semantics slightly if we implement these as mmu_gather. For example, tlb_end_vma() -> tlb_flush_mmu_tlbonly() ends up calling mmu_notifier_invalidate_range() which it didn't before. I think we end up invoking the notifier unnecessarily in some cases (see the comment in __split_huge_pmd()) or we end up calling the notifier twice (e.g. pmdp_huge_clear_flush_notify()). > > Also, I don't see the new flush_pte_* and flush_p4d_* macros used > > anywhere and I don't think they are needed. The pte equivalent is > > flush_tlb_page() (we need to make sure it's not used on a pmd in the > > hugetlb context). > > flush_tlb_page() is used to flush only one page. If we add the > flush_pte_tlb_range(), then we can use it to flush a range of pages in > the future. If we know flush_tlb_page() is only called on a small page, could we add TTL information here as well? > But flush_pte_* and flush_p4d_* macros are really not used anywhere. I > will remove them in next version of series, and add them if someone > needs. I think it makes sense. -- Catalin
WARNING: multiple messages have this Message-ID (diff)
From: Catalin Marinas <catalin.marinas@arm.com> To: Zhenyu Ye <yezhenyu2@huawei.com> Cc: mark.rutland@arm.com, peterz@infradead.org, linux-mm@kvack.org, guohanjun@huawei.com, will@kernel.org, linux-arch@vger.kernel.org, yuzhao@google.com, aneesh.kumar@linux.ibm.com, steven.price@arm.com, arm@kernel.org, Dave.Martin@arm.com, arnd@arndb.de, suzuki.poulose@arm.com, npiggin@gmail.com, zhangshaokun@hisilicon.com, broonie@kernel.org, rostedt@goodmis.org, prime.zeng@hisilicon.com, kuhn.chenqun@huawei.com, tglx@linutronix.de, linux-arm-kernel@lists.infradead.org, xiexiangyou@huawei.com, linux-kernel@vger.kernel.org, maz@kernel.org, akpm@linux-foundation.org Subject: Re: [PATCH v2 5/6] mm: tlb: Provide flush_*_tlb_range wrappers Date: Mon, 1 Jun 2020 12:56:45 +0100 [thread overview] Message-ID: <20200601115644.GA23419@gaia> (raw) In-Reply-To: <0c6f79e4-f29a-d373-2e43-c4f87cf78b49@huawei.com> Hi Zhenyu, On Sat, May 30, 2020 at 06:24:21PM +0800, Zhenyu Ye wrote: > On 2020/5/26 22:52, Catalin Marinas wrote: > > On Mon, May 25, 2020 at 03:19:42PM +0800, Zhenyu Ye wrote: > >> tlb_flush_##_pxx##_range() is used to set tlb->cleared_*, > >> flush_##_pxx##_tlb_range() will actually flush the TLB entry. > >> > >> In arch64, tlb_flush_p?d_range() is defined as: > >> > >> #define flush_pmd_tlb_range(vma, addr, end) flush_tlb_range(vma, addr, end) > >> #define flush_pud_tlb_range(vma, addr, end) flush_tlb_range(vma, addr, end) > > > > Currently, flush_p??_tlb_range() are generic and defined as above. I > > think in the generic code they can remain an alias for > > flush_tlb_range(). > > > > On arm64, we can redefine them as: > > > > #define flush_pte_tlb_range(vma, addr, end) __flush_tlb_range(vma, addr, end, 3) > > #define flush_pmd_tlb_range(vma, addr, end) __flush_tlb_range(vma, addr, end, 2) > > #define flush_pud_tlb_range(vma, addr, end) __flush_tlb_range(vma, addr, end, 1) > > #define flush_p4d_tlb_range(vma, addr, end) __flush_tlb_range(vma, addr, end, 0) > > > > (unless the compiler optimises away all the mmu_gather stuff in your > > macro above but they don't look trivial to me) > > I changed generic code before considering that other structures may also > use this feature, such as Power9. And Peter may want to replace all > flush_tlb_range() by tlb_flush() in the future, see [1] for details. > > If only enable this feature on aarch64, your codes are better. > > [1] https://lore.kernel.org/linux-arm-kernel/20200402163849.GM20713@hirez.programming.kicks-ass.net/ But we change the semantics slightly if we implement these as mmu_gather. For example, tlb_end_vma() -> tlb_flush_mmu_tlbonly() ends up calling mmu_notifier_invalidate_range() which it didn't before. I think we end up invoking the notifier unnecessarily in some cases (see the comment in __split_huge_pmd()) or we end up calling the notifier twice (e.g. pmdp_huge_clear_flush_notify()). > > Also, I don't see the new flush_pte_* and flush_p4d_* macros used > > anywhere and I don't think they are needed. The pte equivalent is > > flush_tlb_page() (we need to make sure it's not used on a pmd in the > > hugetlb context). > > flush_tlb_page() is used to flush only one page. If we add the > flush_pte_tlb_range(), then we can use it to flush a range of pages in > the future. If we know flush_tlb_page() is only called on a small page, could we add TTL information here as well? > But flush_pte_* and flush_p4d_* macros are really not used anywhere. I > will remove them in next version of series, and add them if someone > needs. I think it makes sense. -- Catalin _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-06-01 11:56 UTC|newest] Thread overview: 55+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-04-23 13:56 [PATCH v2 0/6] arm64: tlb: add support for TTL feature Zhenyu Ye 2020-04-23 13:56 ` Zhenyu Ye 2020-04-23 13:56 ` Zhenyu Ye 2020-04-23 13:56 ` [PATCH v2 1/6] arm64: Detect the ARMv8.4 " Zhenyu Ye 2020-04-23 13:56 ` Zhenyu Ye 2020-04-23 13:56 ` Zhenyu Ye 2020-05-22 15:50 ` Catalin Marinas 2020-05-22 15:50 ` Catalin Marinas 2020-04-23 13:56 ` [PATCH v2 2/6] arm64: Add level-hinted TLB invalidation helper Zhenyu Ye 2020-04-23 13:56 ` Zhenyu Ye 2020-04-23 13:56 ` Zhenyu Ye 2020-05-22 15:50 ` Catalin Marinas 2020-05-22 15:50 ` Catalin Marinas 2020-05-25 6:54 ` Zhenyu Ye 2020-05-25 6:54 ` Zhenyu Ye 2020-05-25 6:54 ` Zhenyu Ye 2020-04-23 13:56 ` [PATCH v2 3/6] arm64: Add tlbi_user_level " Zhenyu Ye 2020-04-23 13:56 ` Zhenyu Ye 2020-04-23 13:56 ` Zhenyu Ye 2020-05-22 15:49 ` Catalin Marinas 2020-05-22 15:49 ` Catalin Marinas 2020-05-25 6:57 ` Zhenyu Ye 2020-05-25 6:57 ` Zhenyu Ye 2020-05-25 6:57 ` Zhenyu Ye 2020-04-23 13:56 ` [PATCH v2 4/6] tlb: mmu_gather: add tlb_flush_*_range APIs Zhenyu Ye 2020-04-23 13:56 ` Zhenyu Ye 2020-04-23 13:56 ` Zhenyu Ye 2020-05-22 15:50 ` Catalin Marinas 2020-05-22 15:50 ` Catalin Marinas 2020-04-23 13:56 ` [PATCH v2 5/6] mm: tlb: Provide flush_*_tlb_range wrappers Zhenyu Ye 2020-04-23 13:56 ` Zhenyu Ye 2020-04-23 13:56 ` Zhenyu Ye 2020-05-22 15:42 ` Catalin Marinas 2020-05-22 15:42 ` Catalin Marinas 2020-05-25 7:19 ` Zhenyu Ye 2020-05-25 7:19 ` Zhenyu Ye 2020-05-25 7:19 ` Zhenyu Ye 2020-05-26 14:52 ` Catalin Marinas 2020-05-26 14:52 ` Catalin Marinas 2020-05-30 10:24 ` Zhenyu Ye 2020-05-30 10:24 ` Zhenyu Ye 2020-05-30 10:24 ` Zhenyu Ye 2020-06-01 11:56 ` Catalin Marinas [this message] 2020-06-01 11:56 ` Catalin Marinas 2020-06-01 13:36 ` Zhenyu Ye 2020-06-01 13:36 ` Zhenyu Ye 2020-06-01 13:36 ` Zhenyu Ye 2020-04-23 13:56 ` [PATCH v2 6/6] arm64: tlb: Set the TTL field in flush_tlb_range Zhenyu Ye 2020-04-23 13:56 ` Zhenyu Ye 2020-04-23 13:56 ` Zhenyu Ye 2020-05-26 14:56 ` Catalin Marinas 2020-05-26 14:56 ` Catalin Marinas 2020-05-11 12:41 ` [PATCH v2 0/6] arm64: tlb: add support for TTL feature Zhenyu Ye 2020-05-11 12:41 ` Zhenyu Ye 2020-05-11 12:41 ` Zhenyu Ye
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