From: Vignesh Raghavendra <vigneshr@ti.com> To: Tudor Ambarus <tudor.ambarus@microchip.com>, Mark Brown <broonie@kernel.org> Cc: Vignesh Raghavendra <vigneshr@ti.com>, Boris Brezillon <bbrezillon@kernel.org>, Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>, <linux-mtd@lists.infradead.org>, <linux-kernel@vger.kernel.org>, <linux-spi@vger.kernel.org>, <simon.k.r.goldschmidt@gmail.com>, <dinguyen@kernel.org>, <marex@denx.de> Subject: [RESEND PATCH v3 1/8] mtd: spi-nor: cadence-quadspi: Make driver independent of flash geometry Date: Mon, 1 Jun 2020 12:34:37 +0530 [thread overview] Message-ID: <20200601070444.16923-2-vigneshr@ti.com> (raw) In-Reply-To: <20200601070444.16923-1-vigneshr@ti.com> Drop configuration of Flash size, erase size and page size configuration. Flash size is needed only if using AHB decoder (BIT 23 of CONFIG_REG) which is not used by the driver. Erase size and page size are needed if IP is configured to send WREN automatically. But since SPI NOR layer takes care of sending WREN, there is no need to configure these fields either. Therefore drop these in preparation to move the driver to spi-mem framework where flash geometry is not visible to controller driver. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> --- .../mtd/spi-nor/controllers/cadence-quadspi.c | 36 +------------------ 1 file changed, 1 insertion(+), 35 deletions(-) diff --git a/drivers/mtd/spi-nor/controllers/cadence-quadspi.c b/drivers/mtd/spi-nor/controllers/cadence-quadspi.c index 494dcab4aaaab..9b8554d44fac8 100644 --- a/drivers/mtd/spi-nor/controllers/cadence-quadspi.c +++ b/drivers/mtd/spi-nor/controllers/cadence-quadspi.c @@ -77,9 +77,6 @@ struct cqspi_st { dma_addr_t mmap_phys_base; int current_cs; - int current_page_size; - int current_erase_size; - int current_addr_width; unsigned long master_ref_clk_hz; bool is_decoded_cs; u32 fifo_depth; @@ -736,32 +733,6 @@ static void cqspi_chipselect(struct spi_nor *nor) writel(reg, reg_base + CQSPI_REG_CONFIG); } -static void cqspi_configure_cs_and_sizes(struct spi_nor *nor) -{ - struct cqspi_flash_pdata *f_pdata = nor->priv; - struct cqspi_st *cqspi = f_pdata->cqspi; - void __iomem *iobase = cqspi->iobase; - unsigned int reg; - - /* configure page size and block size. */ - reg = readl(iobase + CQSPI_REG_SIZE); - reg &= ~(CQSPI_REG_SIZE_PAGE_MASK << CQSPI_REG_SIZE_PAGE_LSB); - reg &= ~(CQSPI_REG_SIZE_BLOCK_MASK << CQSPI_REG_SIZE_BLOCK_LSB); - reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK; - reg |= (nor->page_size << CQSPI_REG_SIZE_PAGE_LSB); - reg |= (ilog2(nor->mtd.erasesize) << CQSPI_REG_SIZE_BLOCK_LSB); - reg |= (nor->addr_width - 1); - writel(reg, iobase + CQSPI_REG_SIZE); - - /* configure the chip select */ - cqspi_chipselect(nor); - - /* Store the new configuration of the controller */ - cqspi->current_page_size = nor->page_size; - cqspi->current_erase_size = nor->mtd.erasesize; - cqspi->current_addr_width = nor->addr_width; -} - static unsigned int calculate_ticks_for_ns(const unsigned int ref_clk_hz, const unsigned int ns_val) { @@ -867,18 +838,13 @@ static void cqspi_configure(struct spi_nor *nor) int switch_cs = (cqspi->current_cs != f_pdata->cs); int switch_ck = (cqspi->sclk != sclk); - if ((cqspi->current_page_size != nor->page_size) || - (cqspi->current_erase_size != nor->mtd.erasesize) || - (cqspi->current_addr_width != nor->addr_width)) - switch_cs = 1; - if (switch_cs || switch_ck) cqspi_controller_enable(cqspi, 0); /* Switch chip select. */ if (switch_cs) { cqspi->current_cs = f_pdata->cs; - cqspi_configure_cs_and_sizes(nor); + cqspi_chipselect(nor); } /* Setup baudrate divisor and delays */ -- 2.26.2
WARNING: multiple messages have this Message-ID (diff)
From: Vignesh Raghavendra <vigneshr@ti.com> To: Tudor Ambarus <tudor.ambarus@microchip.com>, Mark Brown <broonie@kernel.org> Cc: marex@denx.de, Vignesh Raghavendra <vigneshr@ti.com>, Boris Brezillon <bbrezillon@kernel.org>, dinguyen@kernel.org, simon.k.r.goldschmidt@gmail.com, linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org, Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>, linux-mtd@lists.infradead.org Subject: [RESEND PATCH v3 1/8] mtd: spi-nor: cadence-quadspi: Make driver independent of flash geometry Date: Mon, 1 Jun 2020 12:34:37 +0530 [thread overview] Message-ID: <20200601070444.16923-2-vigneshr@ti.com> (raw) In-Reply-To: <20200601070444.16923-1-vigneshr@ti.com> Drop configuration of Flash size, erase size and page size configuration. Flash size is needed only if using AHB decoder (BIT 23 of CONFIG_REG) which is not used by the driver. Erase size and page size are needed if IP is configured to send WREN automatically. But since SPI NOR layer takes care of sending WREN, there is no need to configure these fields either. Therefore drop these in preparation to move the driver to spi-mem framework where flash geometry is not visible to controller driver. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> --- .../mtd/spi-nor/controllers/cadence-quadspi.c | 36 +------------------ 1 file changed, 1 insertion(+), 35 deletions(-) diff --git a/drivers/mtd/spi-nor/controllers/cadence-quadspi.c b/drivers/mtd/spi-nor/controllers/cadence-quadspi.c index 494dcab4aaaab..9b8554d44fac8 100644 --- a/drivers/mtd/spi-nor/controllers/cadence-quadspi.c +++ b/drivers/mtd/spi-nor/controllers/cadence-quadspi.c @@ -77,9 +77,6 @@ struct cqspi_st { dma_addr_t mmap_phys_base; int current_cs; - int current_page_size; - int current_erase_size; - int current_addr_width; unsigned long master_ref_clk_hz; bool is_decoded_cs; u32 fifo_depth; @@ -736,32 +733,6 @@ static void cqspi_chipselect(struct spi_nor *nor) writel(reg, reg_base + CQSPI_REG_CONFIG); } -static void cqspi_configure_cs_and_sizes(struct spi_nor *nor) -{ - struct cqspi_flash_pdata *f_pdata = nor->priv; - struct cqspi_st *cqspi = f_pdata->cqspi; - void __iomem *iobase = cqspi->iobase; - unsigned int reg; - - /* configure page size and block size. */ - reg = readl(iobase + CQSPI_REG_SIZE); - reg &= ~(CQSPI_REG_SIZE_PAGE_MASK << CQSPI_REG_SIZE_PAGE_LSB); - reg &= ~(CQSPI_REG_SIZE_BLOCK_MASK << CQSPI_REG_SIZE_BLOCK_LSB); - reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK; - reg |= (nor->page_size << CQSPI_REG_SIZE_PAGE_LSB); - reg |= (ilog2(nor->mtd.erasesize) << CQSPI_REG_SIZE_BLOCK_LSB); - reg |= (nor->addr_width - 1); - writel(reg, iobase + CQSPI_REG_SIZE); - - /* configure the chip select */ - cqspi_chipselect(nor); - - /* Store the new configuration of the controller */ - cqspi->current_page_size = nor->page_size; - cqspi->current_erase_size = nor->mtd.erasesize; - cqspi->current_addr_width = nor->addr_width; -} - static unsigned int calculate_ticks_for_ns(const unsigned int ref_clk_hz, const unsigned int ns_val) { @@ -867,18 +838,13 @@ static void cqspi_configure(struct spi_nor *nor) int switch_cs = (cqspi->current_cs != f_pdata->cs); int switch_ck = (cqspi->sclk != sclk); - if ((cqspi->current_page_size != nor->page_size) || - (cqspi->current_erase_size != nor->mtd.erasesize) || - (cqspi->current_addr_width != nor->addr_width)) - switch_cs = 1; - if (switch_cs || switch_ck) cqspi_controller_enable(cqspi, 0); /* Switch chip select. */ if (switch_cs) { cqspi->current_cs = f_pdata->cs; - cqspi_configure_cs_and_sizes(nor); + cqspi_chipselect(nor); } /* Setup baudrate divisor and delays */ -- 2.26.2 ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/
next prev parent reply other threads:[~2020-06-01 7:05 UTC|newest] Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-06-01 7:04 [RESEND PATCH v3 0/8] mtd: spi-nor: Move cadence-qaudspi to spi-mem framework Vignesh Raghavendra 2020-06-01 7:04 ` Vignesh Raghavendra 2020-06-01 7:04 ` Vignesh Raghavendra [this message] 2020-06-01 7:04 ` [RESEND PATCH v3 1/8] mtd: spi-nor: cadence-quadspi: Make driver independent of flash geometry Vignesh Raghavendra 2020-06-01 7:04 ` [RESEND PATCH v3 2/8] mtd: spi-nor: cadence-quadspi: Provide a way to disable DAC mode Vignesh Raghavendra 2020-06-01 7:04 ` Vignesh Raghavendra 2020-06-01 7:04 ` [RESEND PATCH v3 3/8] mtd: spi-nor: cadence-quadspi: Don't initialize rx_dma_complete on failure Vignesh Raghavendra 2020-06-01 7:04 ` Vignesh Raghavendra 2020-06-01 7:04 ` [RESEND PATCH v3 4/8] mtd: spi-nor: cadence-quadspi: Fix error path on failure to acquire reset lines Vignesh Raghavendra 2020-06-01 7:04 ` Vignesh Raghavendra 2020-06-01 7:04 ` [RESEND PATCH v3 5/8] mtd: spi-nor: cadence-quadspi: Handle probe deferral while requesting DMA channel Vignesh Raghavendra 2020-06-01 7:04 ` Vignesh Raghavendra 2020-08-22 18:05 ` Jan Kiszka 2020-08-22 18:05 ` Jan Kiszka 2020-08-24 11:45 ` Vignesh Raghavendra 2020-08-24 11:45 ` Vignesh Raghavendra 2020-08-24 12:49 ` Jan Kiszka 2020-08-24 12:49 ` Jan Kiszka 2020-08-24 17:20 ` Jan Kiszka 2020-08-24 17:20 ` Jan Kiszka 2020-08-26 10:12 ` Jan Kiszka 2020-08-26 10:12 ` Jan Kiszka 2020-08-26 12:18 ` Vignesh Raghavendra 2020-08-26 12:18 ` Vignesh Raghavendra 2020-08-26 13:31 ` Jan Kiszka 2020-08-26 13:31 ` Jan Kiszka 2020-08-27 7:04 ` Vignesh Raghavendra 2020-08-27 7:04 ` Vignesh Raghavendra 2020-08-25 3:12 ` Jin, Le 2020-08-25 3:12 ` Jin, Le 2020-06-01 7:04 ` [RESEND PATCH v3 6/8] mtd: spi-nor: cadence-quadspi: Drop redundant WREN in erase path Vignesh Raghavendra 2020-06-01 7:04 ` Vignesh Raghavendra 2020-06-01 7:04 ` [RESEND PATCH v3 7/8] mtd: spi-nor: Convert cadence-quadspi to use spi-mem framework Vignesh Raghavendra 2020-06-01 7:04 ` Vignesh Raghavendra 2020-08-24 5:55 ` Jan Kiszka 2020-08-24 5:55 ` Jan Kiszka 2020-08-24 11:44 ` Vignesh Raghavendra 2020-08-24 11:44 ` Vignesh Raghavendra 2020-08-24 12:04 ` Boris Brezillon 2020-08-24 12:04 ` Boris Brezillon 2020-08-24 13:52 ` Jan Kiszka 2020-08-24 13:52 ` Jan Kiszka 2020-08-24 12:06 ` Jan Kiszka 2020-08-24 12:06 ` Jan Kiszka 2020-06-01 7:04 ` [RESEND PATCH v3 8/8] spi: Move cadence-quadspi driver to drivers/spi/ Vignesh Raghavendra 2020-06-01 7:04 ` Vignesh Raghavendra 2020-06-19 10:57 ` [RESEND PATCH v3 0/8] mtd: spi-nor: Move cadence-qaudspi to spi-mem framework Mark Brown 2020-06-19 10:57 ` Mark Brown 2020-06-19 11:47 ` Tudor.Ambarus 2020-06-19 11:47 ` Tudor.Ambarus 2020-06-19 15:17 ` Mark Brown 2020-06-19 15:17 ` Mark Brown 2020-06-26 9:25 ` Tudor.Ambarus 2020-06-26 9:25 ` Tudor.Ambarus 2020-06-19 13:28 ` Mark Brown 2020-06-19 13:28 ` Mark Brown
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