From: Anup Patel <anup.patel@wdc.com>
To: Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
Thomas Gleixner <tglx@linutronix.de>,
Jason Cooper <jason@lakedaemon.net>,
Marc Zyngier <maz@kernel.org>
Cc: Atish Patra <atish.patra@wdc.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
Anup Patel <anup@brainfault.org>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
Anup Patel <anup.patel@wdc.com>
Subject: [PATCH v7 6/6] RISC-V: Force select RISCV_INTC for CONFIG_RISCV
Date: Mon, 1 Jun 2020 14:45:43 +0530 [thread overview]
Message-ID: <20200601091543.943678-7-anup.patel@wdc.com> (raw)
In-Reply-To: <20200601091543.943678-1-anup.patel@wdc.com>
The RISC-V per-HART local interrupt controller driver is mandatory
for all RISC-V system (with/without MMU) hence we force select it
for CONFIG_RISCV (just like RISCV_TIMER).
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
---
arch/riscv/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 822cb0e1a380..2cf0c83c1a47 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -51,6 +51,7 @@ config RISCV
select THREAD_INFO_IN_TASK
select PCI_DOMAINS_GENERIC if PCI
select PCI_MSI if PCI
+ select RISCV_INTC
select RISCV_TIMER
select GENERIC_IRQ_MULTI_HANDLER
select GENERIC_ARCH_TOPOLOGY if SMP
--
2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Anup Patel <anup.patel@wdc.com>
To: Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
Thomas Gleixner <tglx@linutronix.de>,
Jason Cooper <jason@lakedaemon.net>,
Marc Zyngier <maz@kernel.org>
Cc: Anup Patel <anup@brainfault.org>, Anup Patel <anup.patel@wdc.com>,
linux-kernel@vger.kernel.org, Atish Patra <atish.patra@wdc.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
linux-riscv@lists.infradead.org
Subject: [PATCH v7 6/6] RISC-V: Force select RISCV_INTC for CONFIG_RISCV
Date: Mon, 1 Jun 2020 14:45:43 +0530 [thread overview]
Message-ID: <20200601091543.943678-7-anup.patel@wdc.com> (raw)
In-Reply-To: <20200601091543.943678-1-anup.patel@wdc.com>
The RISC-V per-HART local interrupt controller driver is mandatory
for all RISC-V system (with/without MMU) hence we force select it
for CONFIG_RISCV (just like RISCV_TIMER).
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
---
arch/riscv/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 822cb0e1a380..2cf0c83c1a47 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -51,6 +51,7 @@ config RISCV
select THREAD_INFO_IN_TASK
select PCI_DOMAINS_GENERIC if PCI
select PCI_MSI if PCI
+ select RISCV_INTC
select RISCV_TIMER
select GENERIC_IRQ_MULTI_HANDLER
select GENERIC_ARCH_TOPOLOGY if SMP
--
2.25.1
next prev parent reply other threads:[~2020-06-01 9:16 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-01 9:15 [PATCH v7 0/6] New RISC-V Local Interrupt Controller Driver Anup Patel
2020-06-01 9:15 ` Anup Patel
2020-06-01 9:15 ` [PATCH v7 1/6] RISC-V: self-contained IPI handling routine Anup Patel
2020-06-01 9:15 ` Anup Patel
2020-06-01 9:15 ` [PATCH v7 2/6] RISC-V: Rename and move plic_find_hart_id() to arch directory Anup Patel
2020-06-01 9:15 ` Anup Patel
2020-06-01 9:15 ` [PATCH v7 3/6] irqchip: RISC-V per-HART local interrupt controller driver Anup Patel
2020-06-01 9:15 ` Anup Patel
2020-06-01 9:45 ` Marc Zyngier
2020-06-01 9:45 ` Marc Zyngier
2020-06-01 20:19 ` Atish Patra
2020-06-01 20:19 ` Atish Patra
2020-06-02 5:33 ` Anup Patel
2020-06-02 5:33 ` Anup Patel
2020-06-01 9:15 ` [PATCH v7 4/6] clocksource/drivers/timer-riscv: Use per-CPU timer interrupt Anup Patel
2020-06-01 9:15 ` Anup Patel
2020-06-01 9:46 ` Marc Zyngier
2020-06-01 9:46 ` Marc Zyngier
2020-06-01 9:15 ` [PATCH v7 5/6] RISC-V: Remove do_IRQ() function Anup Patel
2020-06-01 9:15 ` Anup Patel
2020-06-01 9:15 ` Anup Patel [this message]
2020-06-01 9:15 ` [PATCH v7 6/6] RISC-V: Force select RISCV_INTC for CONFIG_RISCV Anup Patel
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20200601091543.943678-7-anup.patel@wdc.com \
--to=anup.patel@wdc.com \
--cc=Alistair.Francis@wdc.com \
--cc=anup@brainfault.org \
--cc=aou@eecs.berkeley.edu \
--cc=atish.patra@wdc.com \
--cc=daniel.lezcano@linaro.org \
--cc=jason@lakedaemon.net \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=maz@kernel.org \
--cc=palmer@dabbelt.com \
--cc=paul.walmsley@sifive.com \
--cc=tglx@linutronix.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.