From: Dmitry Osipenko <digetx@gmail.com> To: Thierry Reding <thierry.reding@gmail.com>, Jonathan Hunter <jonathanh@nvidia.com>, Georgi Djakov <georgi.djakov@linaro.org>, Rob Herring <robh+dt@kernel.org>, Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Peter De Schrijver <pdeschrijver@nvidia.com>, MyungJoo Ham <myungjoo.ham@samsung.com>, Kyungmin Park <kyungmin.park@samsung.com>, Chanwoo Choi <cw00.choi@samsung.com>, Mikko Perttunen <cyndis@kapsi.fi> Cc: "Artur Świgoń" <a.swigon@samsung.com>, linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v3 02/39] clk: tegra: Remove Memory Controller lock Date: Sun, 7 Jun 2020 21:54:53 +0300 [thread overview] Message-ID: <20200607185530.18113-3-digetx@gmail.com> (raw) In-Reply-To: <20200607185530.18113-1-digetx@gmail.com> The shared Memory Controller lock isn't needed since the time when Memory Clock was made read-only. The lock could be removed safely now. Hence let's remove it, this will help a tad to make further patches cleaner. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> --- drivers/clk/tegra/clk-divider.c | 4 ++-- drivers/clk/tegra/clk-tegra114.c | 6 ++---- drivers/clk/tegra/clk-tegra124.c | 7 ++----- drivers/clk/tegra/clk-tegra20.c | 3 +-- drivers/clk/tegra/clk-tegra30.c | 3 +-- drivers/clk/tegra/clk.h | 2 +- 6 files changed, 9 insertions(+), 16 deletions(-) diff --git a/drivers/clk/tegra/clk-divider.c b/drivers/clk/tegra/clk-divider.c index 38daf483ddf1..56adb01638cc 100644 --- a/drivers/clk/tegra/clk-divider.c +++ b/drivers/clk/tegra/clk-divider.c @@ -177,10 +177,10 @@ static const struct clk_div_table mc_div_table[] = { }; struct clk *tegra_clk_register_mc(const char *name, const char *parent_name, - void __iomem *reg, spinlock_t *lock) + void __iomem *reg) { return clk_register_divider_table(NULL, name, parent_name, CLK_IS_CRITICAL, reg, 16, 1, CLK_DIVIDER_READ_ONLY, - mc_div_table, lock); + mc_div_table, NULL); } diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c index bc9e47a4cb60..ca8d9737d301 100644 --- a/drivers/clk/tegra/clk-tegra114.c +++ b/drivers/clk/tegra/clk-tegra114.c @@ -134,7 +134,6 @@ static DEFINE_SPINLOCK(pll_d_lock); static DEFINE_SPINLOCK(pll_d2_lock); static DEFINE_SPINLOCK(pll_u_lock); static DEFINE_SPINLOCK(pll_re_lock); -static DEFINE_SPINLOCK(emc_lock); static struct div_nmp pllxc_nmp = { .divm_shift = 0, @@ -1050,10 +1049,9 @@ static __init void tegra114_periph_clk_init(void __iomem *clk_base, ARRAY_SIZE(mux_pllmcp_clkm), CLK_SET_RATE_NO_REPARENT, clk_base + CLK_SOURCE_EMC, - 29, 3, 0, &emc_lock); + 29, 3, 0, NULL); - clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC, - &emc_lock); + clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC); clks[TEGRA114_CLK_MC] = clk; clk = tegra_clk_register_periph_gate("mipi-cal", "clk_m", 0, clk_base, diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c index e931319dcc9d..0c956e14b9ca 100644 --- a/drivers/clk/tegra/clk-tegra124.c +++ b/drivers/clk/tegra/clk-tegra124.c @@ -126,7 +126,6 @@ static DEFINE_SPINLOCK(pll_d_lock); static DEFINE_SPINLOCK(pll_e_lock); static DEFINE_SPINLOCK(pll_re_lock); static DEFINE_SPINLOCK(pll_u_lock); -static DEFINE_SPINLOCK(emc_lock); static DEFINE_SPINLOCK(sor0_lock); /* possible OSC frequencies in Hz */ @@ -1050,8 +1049,7 @@ static __init void tegra124_periph_clk_init(void __iomem *clk_base, periph_clk_enb_refcnt); clks[TEGRA124_CLK_DSIB] = clk; - clk = tegra_clk_register_mc("mc", "emc", clk_base + CLK_SOURCE_EMC, - &emc_lock); + clk = tegra_clk_register_mc("mc", "emc", clk_base + CLK_SOURCE_EMC); clks[TEGRA124_CLK_MC] = clk; /* cml0 */ @@ -1518,8 +1516,7 @@ static void __init tegra124_132_clock_init_post(struct device_node *np) tegra124_reset_deassert); tegra_add_of_provider(np, of_clk_src_onecell_get); - clks[TEGRA124_CLK_EMC] = tegra_clk_register_emc(clk_base, np, - &emc_lock); + clks[TEGRA124_CLK_EMC] = tegra_clk_register_emc(clk_base, np, NULL); tegra_register_devclks(devclks, ARRAY_SIZE(devclks)); diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c index 3efc651b42e3..2f8b6de4198f 100644 --- a/drivers/clk/tegra/clk-tegra20.c +++ b/drivers/clk/tegra/clk-tegra20.c @@ -802,8 +802,7 @@ static void __init tegra20_periph_clk_init(void) clks[TEGRA20_CLK_EMC] = clk; - clk = tegra_clk_register_mc("mc", "emc", clk_base + CLK_SOURCE_EMC, - NULL); + clk = tegra_clk_register_mc("mc", "emc", clk_base + CLK_SOURCE_EMC); clks[TEGRA20_CLK_MC] = clk; /* dsi */ diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c index 37244a7e68c2..88e8c485f8ae 100644 --- a/drivers/clk/tegra/clk-tegra30.c +++ b/drivers/clk/tegra/clk-tegra30.c @@ -1042,8 +1042,7 @@ static void __init tegra30_periph_clk_init(void) clks[TEGRA30_CLK_EMC] = clk; - clk = tegra_clk_register_mc("mc", "emc", clk_base + CLK_SOURCE_EMC, - NULL); + clk = tegra_clk_register_mc("mc", "emc", clk_base + CLK_SOURCE_EMC); clks[TEGRA30_CLK_MC] = clk; /* cml0 */ diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index 6b565f6b5f66..5ed8b95d331c 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -136,7 +136,7 @@ struct clk *tegra_clk_register_divider(const char *name, unsigned long flags, u8 clk_divider_flags, u8 shift, u8 width, u8 frac_width, spinlock_t *lock); struct clk *tegra_clk_register_mc(const char *name, const char *parent_name, - void __iomem *reg, spinlock_t *lock); + void __iomem *reg); /* * Tegra PLL: -- 2.26.0
WARNING: multiple messages have this Message-ID (diff)
From: Dmitry Osipenko <digetx@gmail.com> To: Thierry Reding <thierry.reding@gmail.com>, Jonathan Hunter <jonathanh@nvidia.com>, Georgi Djakov <georgi.djakov@linaro.org>, Rob Herring <robh+dt@kernel.org>, Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Peter De Schrijver <pdeschrijver@nvidia.com>, MyungJoo Ham <myungjoo.ham@samsung.com>, Kyungmin Park <kyungmin.park@samsung.com>, Chanwoo Choi <cw00.choi@samsung.com>, Mikko Perttunen <cyndis@kapsi.fi> Cc: devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, "Artur Świgoń" <a.swigon@samsung.com>, linux-tegra@vger.kernel.org Subject: [PATCH v3 02/39] clk: tegra: Remove Memory Controller lock Date: Sun, 7 Jun 2020 21:54:53 +0300 [thread overview] Message-ID: <20200607185530.18113-3-digetx@gmail.com> (raw) In-Reply-To: <20200607185530.18113-1-digetx@gmail.com> The shared Memory Controller lock isn't needed since the time when Memory Clock was made read-only. The lock could be removed safely now. Hence let's remove it, this will help a tad to make further patches cleaner. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> --- drivers/clk/tegra/clk-divider.c | 4 ++-- drivers/clk/tegra/clk-tegra114.c | 6 ++---- drivers/clk/tegra/clk-tegra124.c | 7 ++----- drivers/clk/tegra/clk-tegra20.c | 3 +-- drivers/clk/tegra/clk-tegra30.c | 3 +-- drivers/clk/tegra/clk.h | 2 +- 6 files changed, 9 insertions(+), 16 deletions(-) diff --git a/drivers/clk/tegra/clk-divider.c b/drivers/clk/tegra/clk-divider.c index 38daf483ddf1..56adb01638cc 100644 --- a/drivers/clk/tegra/clk-divider.c +++ b/drivers/clk/tegra/clk-divider.c @@ -177,10 +177,10 @@ static const struct clk_div_table mc_div_table[] = { }; struct clk *tegra_clk_register_mc(const char *name, const char *parent_name, - void __iomem *reg, spinlock_t *lock) + void __iomem *reg) { return clk_register_divider_table(NULL, name, parent_name, CLK_IS_CRITICAL, reg, 16, 1, CLK_DIVIDER_READ_ONLY, - mc_div_table, lock); + mc_div_table, NULL); } diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c index bc9e47a4cb60..ca8d9737d301 100644 --- a/drivers/clk/tegra/clk-tegra114.c +++ b/drivers/clk/tegra/clk-tegra114.c @@ -134,7 +134,6 @@ static DEFINE_SPINLOCK(pll_d_lock); static DEFINE_SPINLOCK(pll_d2_lock); static DEFINE_SPINLOCK(pll_u_lock); static DEFINE_SPINLOCK(pll_re_lock); -static DEFINE_SPINLOCK(emc_lock); static struct div_nmp pllxc_nmp = { .divm_shift = 0, @@ -1050,10 +1049,9 @@ static __init void tegra114_periph_clk_init(void __iomem *clk_base, ARRAY_SIZE(mux_pllmcp_clkm), CLK_SET_RATE_NO_REPARENT, clk_base + CLK_SOURCE_EMC, - 29, 3, 0, &emc_lock); + 29, 3, 0, NULL); - clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC, - &emc_lock); + clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC); clks[TEGRA114_CLK_MC] = clk; clk = tegra_clk_register_periph_gate("mipi-cal", "clk_m", 0, clk_base, diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c index e931319dcc9d..0c956e14b9ca 100644 --- a/drivers/clk/tegra/clk-tegra124.c +++ b/drivers/clk/tegra/clk-tegra124.c @@ -126,7 +126,6 @@ static DEFINE_SPINLOCK(pll_d_lock); static DEFINE_SPINLOCK(pll_e_lock); static DEFINE_SPINLOCK(pll_re_lock); static DEFINE_SPINLOCK(pll_u_lock); -static DEFINE_SPINLOCK(emc_lock); static DEFINE_SPINLOCK(sor0_lock); /* possible OSC frequencies in Hz */ @@ -1050,8 +1049,7 @@ static __init void tegra124_periph_clk_init(void __iomem *clk_base, periph_clk_enb_refcnt); clks[TEGRA124_CLK_DSIB] = clk; - clk = tegra_clk_register_mc("mc", "emc", clk_base + CLK_SOURCE_EMC, - &emc_lock); + clk = tegra_clk_register_mc("mc", "emc", clk_base + CLK_SOURCE_EMC); clks[TEGRA124_CLK_MC] = clk; /* cml0 */ @@ -1518,8 +1516,7 @@ static void __init tegra124_132_clock_init_post(struct device_node *np) tegra124_reset_deassert); tegra_add_of_provider(np, of_clk_src_onecell_get); - clks[TEGRA124_CLK_EMC] = tegra_clk_register_emc(clk_base, np, - &emc_lock); + clks[TEGRA124_CLK_EMC] = tegra_clk_register_emc(clk_base, np, NULL); tegra_register_devclks(devclks, ARRAY_SIZE(devclks)); diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c index 3efc651b42e3..2f8b6de4198f 100644 --- a/drivers/clk/tegra/clk-tegra20.c +++ b/drivers/clk/tegra/clk-tegra20.c @@ -802,8 +802,7 @@ static void __init tegra20_periph_clk_init(void) clks[TEGRA20_CLK_EMC] = clk; - clk = tegra_clk_register_mc("mc", "emc", clk_base + CLK_SOURCE_EMC, - NULL); + clk = tegra_clk_register_mc("mc", "emc", clk_base + CLK_SOURCE_EMC); clks[TEGRA20_CLK_MC] = clk; /* dsi */ diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c index 37244a7e68c2..88e8c485f8ae 100644 --- a/drivers/clk/tegra/clk-tegra30.c +++ b/drivers/clk/tegra/clk-tegra30.c @@ -1042,8 +1042,7 @@ static void __init tegra30_periph_clk_init(void) clks[TEGRA30_CLK_EMC] = clk; - clk = tegra_clk_register_mc("mc", "emc", clk_base + CLK_SOURCE_EMC, - NULL); + clk = tegra_clk_register_mc("mc", "emc", clk_base + CLK_SOURCE_EMC); clks[TEGRA30_CLK_MC] = clk; /* cml0 */ diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index 6b565f6b5f66..5ed8b95d331c 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -136,7 +136,7 @@ struct clk *tegra_clk_register_divider(const char *name, unsigned long flags, u8 clk_divider_flags, u8 shift, u8 width, u8 frac_width, spinlock_t *lock); struct clk *tegra_clk_register_mc(const char *name, const char *parent_name, - void __iomem *reg, spinlock_t *lock); + void __iomem *reg); /* * Tegra PLL: -- 2.26.0 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
next prev parent reply other threads:[~2020-06-07 18:54 UTC|newest] Thread overview: 122+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-06-07 18:54 [PATCH v3 00/39] Introduce memory interconnect for NVIDIA Tegra SoCs Dmitry Osipenko 2020-06-07 18:54 ` Dmitry Osipenko 2020-06-07 18:54 ` Dmitry Osipenko 2020-06-07 18:54 ` Dmitry Osipenko [this message] 2020-06-07 18:54 ` [PATCH v3 02/39] clk: tegra: Remove Memory Controller lock Dmitry Osipenko 2020-06-07 18:55 ` [PATCH v3 12/39] PM / devfreq: tegra20: Use MC timings for building OPP table Dmitry Osipenko 2020-06-07 18:55 ` Dmitry Osipenko 2020-06-07 18:55 ` [PATCH v3 13/39] PM / devfreq: tegra30: " Dmitry Osipenko 2020-06-07 18:55 ` Dmitry Osipenko 2020-06-07 18:55 ` [PATCH v3 17/39] PM / devfreq: tegra20: Relax Kconfig dependency Dmitry Osipenko 2020-06-07 18:55 ` Dmitry Osipenko 2020-06-07 18:55 ` [PATCH v3 19/39] dt-bindings: memory: tegra20: emc: Document new interconnect property Dmitry Osipenko 2020-06-07 18:55 ` Dmitry Osipenko 2020-06-07 18:55 ` [PATCH v3 22/39] dt-bindings: host1x: Document new interconnect properties Dmitry Osipenko 2020-06-07 18:55 ` Dmitry Osipenko 2020-06-07 18:55 ` [PATCH v3 30/39] memory: tegra20-emc: Continue probing if timings are missing in device-tree Dmitry Osipenko 2020-06-07 18:55 ` Dmitry Osipenko 2020-06-07 18:55 ` [PATCH v3 33/39] memory: tegra30-emc: " Dmitry Osipenko 2020-06-07 18:55 ` Dmitry Osipenko 2020-06-07 18:55 ` [PATCH v3 34/39] memory: tegra30-emc: Register as interconnect provider Dmitry Osipenko 2020-06-07 18:55 ` Dmitry Osipenko [not found] ` <20200607185530.18113-1-digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> 2020-06-07 18:54 ` [PATCH v3 01/39] clk: Export clk_hw_reparent() Dmitry Osipenko 2020-06-07 18:54 ` Dmitry Osipenko 2020-06-07 18:54 ` Dmitry Osipenko 2020-06-07 18:54 ` [PATCH v3 03/39] clk: tegra: Export Tegra20 EMC kernel symbols Dmitry Osipenko 2020-06-07 18:54 ` Dmitry Osipenko 2020-06-07 18:54 ` Dmitry Osipenko 2020-06-07 18:54 ` [PATCH v3 04/39] memory: tegra20-emc: Make driver modular Dmitry Osipenko 2020-06-07 18:54 ` Dmitry Osipenko 2020-06-07 18:54 ` Dmitry Osipenko 2020-06-07 18:54 ` [PATCH v3 05/39] memory: tegra30-emc: " Dmitry Osipenko 2020-06-07 18:54 ` Dmitry Osipenko 2020-06-07 18:54 ` Dmitry Osipenko 2020-06-07 18:54 ` [PATCH v3 06/39] memory: tegra124-emc: " Dmitry Osipenko 2020-06-07 18:54 ` Dmitry Osipenko 2020-06-07 18:54 ` Dmitry Osipenko 2020-06-07 18:54 ` [PATCH v3 07/39] memory: tegra124-emc: Use devm_platform_ioremap_resource Dmitry Osipenko 2020-06-07 18:54 ` Dmitry Osipenko 2020-06-07 18:54 ` Dmitry Osipenko 2020-06-07 18:54 ` [PATCH v3 08/39] soc/tegra: fuse: Export tegra_read_ram_code() Dmitry Osipenko 2020-06-07 18:54 ` Dmitry Osipenko 2020-06-07 18:54 ` Dmitry Osipenko 2020-06-07 18:55 ` [PATCH v3 09/39] memory: tegra20-emc: Initialize MC timings Dmitry Osipenko 2020-06-07 18:55 ` Dmitry Osipenko 2020-06-07 18:55 ` Dmitry Osipenko 2020-06-07 18:55 ` [PATCH v3 10/39] PM / devfreq: tegra20: Silence deferred probe error Dmitry Osipenko 2020-06-07 18:55 ` Dmitry Osipenko 2020-06-07 18:55 ` Dmitry Osipenko 2020-06-07 18:55 ` [PATCH v3 11/39] PM / devfreq: tegra30: " Dmitry Osipenko 2020-06-07 18:55 ` Dmitry Osipenko 2020-06-07 18:55 ` Dmitry Osipenko 2020-06-07 18:55 ` [PATCH v3 14/39] PM / devfreq: tegra20: Add error messages to tegra_devfreq_target() Dmitry Osipenko 2020-06-07 18:55 ` Dmitry Osipenko 2020-06-07 18:55 ` Dmitry Osipenko 2020-06-07 18:55 ` [PATCH v3 15/39] PM / devfreq: tegra30: " Dmitry Osipenko 2020-06-07 18:55 ` Dmitry Osipenko 2020-06-07 18:55 ` Dmitry Osipenko 2020-06-07 18:55 ` [PATCH v3 16/39] PM / devfreq: tegra20: Adjust clocks conversion ratio and polling interval Dmitry Osipenko 2020-06-07 18:55 ` Dmitry Osipenko 2020-06-07 18:55 ` Dmitry Osipenko 2020-06-07 18:55 ` [PATCH v3 18/39] dt-bindings: memory: tegra20: mc: Document new interconnect property Dmitry Osipenko 2020-06-07 18:55 ` Dmitry Osipenko 2020-06-07 18:55 ` Dmitry Osipenko 2020-06-07 18:55 ` [PATCH v3 20/39] dt-bindings: memory: tegra30: " Dmitry Osipenko 2020-06-07 18:55 ` Dmitry Osipenko 2020-06-07 18:55 ` Dmitry Osipenko 2020-06-07 18:55 ` [PATCH v3 21/39] dt-bindings: memory: tegra30: emc: " Dmitry Osipenko 2020-06-07 18:55 ` Dmitry Osipenko 2020-06-07 18:55 ` Dmitry Osipenko 2020-06-07 18:55 ` [PATCH v3 23/39] dt-bindings: memory: tegra20: Add memory client IDs Dmitry Osipenko 2020-06-07 18:55 ` Dmitry Osipenko 2020-06-07 18:55 ` Dmitry Osipenko [not found] ` <20200607185530.18113-24-digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> 2020-06-09 20:01 ` Rob Herring 2020-06-09 20:01 ` Rob Herring 2020-06-09 20:01 ` Rob Herring 2020-06-07 18:55 ` [PATCH v3 24/39] dt-bindings: memory: tegra30: " Dmitry Osipenko 2020-06-07 18:55 ` Dmitry Osipenko 2020-06-07 18:55 ` Dmitry Osipenko [not found] ` <20200607185530.18113-25-digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> 2020-06-09 20:02 ` Rob Herring 2020-06-09 20:02 ` Rob Herring 2020-06-09 20:02 ` Rob Herring 2020-06-07 18:55 ` [PATCH v3 25/39] ARM: tegra: Add interconnect properties to Tegra20 device-tree Dmitry Osipenko 2020-06-07 18:55 ` Dmitry Osipenko 2020-06-07 18:55 ` Dmitry Osipenko 2020-06-07 18:55 ` [PATCH v3 26/39] ARM: tegra: Add interconnect properties to Tegra30 device-tree Dmitry Osipenko 2020-06-07 18:55 ` Dmitry Osipenko 2020-06-07 18:55 ` Dmitry Osipenko 2020-06-07 18:55 ` [PATCH v3 27/39] interconnect: Relax requirement in of_icc_get_from_provider() Dmitry Osipenko 2020-06-07 18:55 ` Dmitry Osipenko 2020-06-07 18:55 ` Dmitry Osipenko 2020-06-07 18:55 ` [PATCH v3 28/39] memory: tegra: Register as interconnect provider Dmitry Osipenko 2020-06-07 18:55 ` Dmitry Osipenko 2020-06-07 18:55 ` Dmitry Osipenko 2020-06-07 23:06 ` kernel test robot 2020-06-07 23:38 ` kernel test robot 2020-06-08 0:13 ` kernel test robot 2020-06-07 18:55 ` [PATCH v3 29/39] memory: tegra20-emc: Use devm_platform_ioremap_resource Dmitry Osipenko 2020-06-07 18:55 ` Dmitry Osipenko 2020-06-07 18:55 ` Dmitry Osipenko 2020-06-07 18:55 ` [PATCH v3 31/39] memory: tegra20-emc: Register as interconnect provider Dmitry Osipenko 2020-06-07 18:55 ` Dmitry Osipenko 2020-06-07 18:55 ` Dmitry Osipenko [not found] ` <20200607185530.18113-32-digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> 2020-06-07 21:47 ` Dmitry Osipenko 2020-06-07 21:47 ` Dmitry Osipenko 2020-06-07 21:47 ` Dmitry Osipenko 2020-06-07 18:55 ` [PATCH v3 32/39] memory: tegra20-emc: Create tegra20-devfreq device Dmitry Osipenko 2020-06-07 18:55 ` Dmitry Osipenko 2020-06-07 18:55 ` Dmitry Osipenko 2020-06-07 18:55 ` [PATCH v3 35/39] drm/tegra: dc: Support memory bandwidth management Dmitry Osipenko 2020-06-07 18:55 ` Dmitry Osipenko 2020-06-07 18:55 ` Dmitry Osipenko 2020-06-07 18:55 ` [PATCH v3 36/39] drm/tegra: dc: Tune up high priority request controls for Tegra20 Dmitry Osipenko 2020-06-07 18:55 ` Dmitry Osipenko 2020-06-07 18:55 ` Dmitry Osipenko 2020-06-07 18:55 ` [PATCH v3 37/39] drm/tegra: dc: Extend debug stats with total number of events Dmitry Osipenko 2020-06-07 18:55 ` Dmitry Osipenko 2020-06-07 18:55 ` Dmitry Osipenko 2020-06-07 18:55 ` [PATCH v3 39/39] ARM: multi_v7_defconfig: Enable interconnect API Dmitry Osipenko 2020-06-07 18:55 ` Dmitry Osipenko 2020-06-07 18:55 ` Dmitry Osipenko 2020-06-07 18:55 ` [PATCH v3 38/39] ARM: tegra: Enable interconnect API in tegra_defconfig Dmitry Osipenko 2020-06-07 18:55 ` Dmitry Osipenko
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20200607185530.18113-3-digetx@gmail.com \ --to=digetx@gmail.com \ --cc=a.swigon@samsung.com \ --cc=cw00.choi@samsung.com \ --cc=cyndis@kapsi.fi \ --cc=devicetree@vger.kernel.org \ --cc=dri-devel@lists.freedesktop.org \ --cc=georgi.djakov@linaro.org \ --cc=jonathanh@nvidia.com \ --cc=kyungmin.park@samsung.com \ --cc=linux-kernel@vger.kernel.org \ --cc=linux-pm@vger.kernel.org \ --cc=linux-tegra@vger.kernel.org \ --cc=mturquette@baylibre.com \ --cc=myungjoo.ham@samsung.com \ --cc=pdeschrijver@nvidia.com \ --cc=robh+dt@kernel.org \ --cc=sboyd@kernel.org \ --cc=thierry.reding@gmail.com \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.