From: Dmitry Osipenko <digetx@gmail.com> To: Thierry Reding <thierry.reding@gmail.com>, Jonathan Hunter <jonathanh@nvidia.com>, Georgi Djakov <georgi.djakov@linaro.org>, Rob Herring <robh+dt@kernel.org>, Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Peter De Schrijver <pdeschrijver@nvidia.com>, MyungJoo Ham <myungjoo.ham@samsung.com>, Kyungmin Park <kyungmin.park@samsung.com>, Chanwoo Choi <cw00.choi@samsung.com>, Mikko Perttunen <cyndis@kapsi.fi> Cc: "Artur Świgoń" <a.swigon@samsung.com>, linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v4 24/37] dt-bindings: memory: tegra30: Add memory client IDs Date: Tue, 9 Jun 2020 16:13:51 +0300 [thread overview] Message-ID: <20200609131404.17523-25-digetx@gmail.com> (raw) In-Reply-To: <20200609131404.17523-1-digetx@gmail.com> Each memory client have a unique hardware ID, this patch adds these IDs. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> --- include/dt-bindings/memory/tegra30-mc.h | 67 +++++++++++++++++++++++++ 1 file changed, 67 insertions(+) diff --git a/include/dt-bindings/memory/tegra30-mc.h b/include/dt-bindings/memory/tegra30-mc.h index 169f005fbc78..930f708aca17 100644 --- a/include/dt-bindings/memory/tegra30-mc.h +++ b/include/dt-bindings/memory/tegra30-mc.h @@ -41,4 +41,71 @@ #define TEGRA30_MC_RESET_VDE 16 #define TEGRA30_MC_RESET_VI 17 +#define TEGRA30_MC_PTCR 0 +#define TEGRA30_MC_DISPLAY0A 1 +#define TEGRA30_MC_DISPLAY0AB 2 +#define TEGRA30_MC_DISPLAY0B 3 +#define TEGRA30_MC_DISPLAY0BB 4 +#define TEGRA30_MC_DISPLAY0C 5 +#define TEGRA30_MC_DISPLAY0CB 6 +#define TEGRA30_MC_DISPLAY1B 7 +#define TEGRA30_MC_DISPLAY1BB 8 +#define TEGRA30_MC_EPPUP 9 +#define TEGRA30_MC_G2PR 10 +#define TEGRA30_MC_G2SR 11 +#define TEGRA30_MC_MPEUNIFBR 12 +#define TEGRA30_MC_VIRUV 13 +#define TEGRA30_MC_AFIR 14 +#define TEGRA30_MC_AVPCARM7R 15 +#define TEGRA30_MC_DISPLAYHC 16 +#define TEGRA30_MC_DISPLAYHCB 17 +#define TEGRA30_MC_FDCDRD 18 +#define TEGRA30_MC_FDCDRD2 19 +#define TEGRA30_MC_G2DR 20 +#define TEGRA30_MC_HDAR 21 +#define TEGRA30_MC_HOST1XDMAR 22 +#define TEGRA30_MC_HOST1XR 23 +#define TEGRA30_MC_IDXSRD 24 +#define TEGRA30_MC_IDXSRD2 25 +#define TEGRA30_MC_MPE_IPRED 26 +#define TEGRA30_MC_MPEAMEMRD 27 +#define TEGRA30_MC_MPECSRD 28 +#define TEGRA30_MC_PPCSAHBDMAR 29 +#define TEGRA30_MC_PPCSAHBSLVR 30 +#define TEGRA30_MC_SATAR 31 +#define TEGRA30_MC_TEXSRD 32 +#define TEGRA30_MC_TEXSRD2 33 +#define TEGRA30_MC_VDEBSEVR 34 +#define TEGRA30_MC_VDEMBER 35 +#define TEGRA30_MC_VDEMCER 36 +#define TEGRA30_MC_VDETPER 37 +#define TEGRA30_MC_MPCORELPR 38 +#define TEGRA30_MC_MPCORER 39 +#define TEGRA30_MC_EPPU 40 +#define TEGRA30_MC_EPPV 41 +#define TEGRA30_MC_EPPY 42 +#define TEGRA30_MC_MPEUNIFBW 43 +#define TEGRA30_MC_VIWSB 44 +#define TEGRA30_MC_VIWU 45 +#define TEGRA30_MC_VIWV 46 +#define TEGRA30_MC_VIWY 47 +#define TEGRA30_MC_G2DW 48 +#define TEGRA30_MC_AFIW 49 +#define TEGRA30_MC_AVPCARM7W 50 +#define TEGRA30_MC_FDCDWR 51 +#define TEGRA30_MC_FDCDWR2 52 +#define TEGRA30_MC_HDAW 53 +#define TEGRA30_MC_HOST1XW 54 +#define TEGRA30_MC_ISPW 55 +#define TEGRA30_MC_MPCORELPW 56 +#define TEGRA30_MC_MPCOREW 57 +#define TEGRA30_MC_MPECSWR 58 +#define TEGRA30_MC_PPCSAHBDMAW 59 +#define TEGRA30_MC_PPCSAHBSLVW 60 +#define TEGRA30_MC_SATAW 61 +#define TEGRA30_MC_VDEBSEVW 62 +#define TEGRA30_MC_VDEDBGW 63 +#define TEGRA30_MC_VDEMBEW 64 +#define TEGRA30_MC_VDETPMW 65 + #endif -- 2.26.0
WARNING: multiple messages have this Message-ID (diff)
From: Dmitry Osipenko <digetx@gmail.com> To: Thierry Reding <thierry.reding@gmail.com>, Jonathan Hunter <jonathanh@nvidia.com>, Georgi Djakov <georgi.djakov@linaro.org>, Rob Herring <robh+dt@kernel.org>, Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Peter De Schrijver <pdeschrijver@nvidia.com>, MyungJoo Ham <myungjoo.ham@samsung.com>, Kyungmin Park <kyungmin.park@samsung.com>, Chanwoo Choi <cw00.choi@samsung.com>, Mikko Perttunen <cyndis@kapsi.fi> Cc: devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, "Artur Świgoń" <a.swigon@samsung.com>, linux-tegra@vger.kernel.org Subject: [PATCH v4 24/37] dt-bindings: memory: tegra30: Add memory client IDs Date: Tue, 9 Jun 2020 16:13:51 +0300 [thread overview] Message-ID: <20200609131404.17523-25-digetx@gmail.com> (raw) In-Reply-To: <20200609131404.17523-1-digetx@gmail.com> Each memory client have a unique hardware ID, this patch adds these IDs. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> --- include/dt-bindings/memory/tegra30-mc.h | 67 +++++++++++++++++++++++++ 1 file changed, 67 insertions(+) diff --git a/include/dt-bindings/memory/tegra30-mc.h b/include/dt-bindings/memory/tegra30-mc.h index 169f005fbc78..930f708aca17 100644 --- a/include/dt-bindings/memory/tegra30-mc.h +++ b/include/dt-bindings/memory/tegra30-mc.h @@ -41,4 +41,71 @@ #define TEGRA30_MC_RESET_VDE 16 #define TEGRA30_MC_RESET_VI 17 +#define TEGRA30_MC_PTCR 0 +#define TEGRA30_MC_DISPLAY0A 1 +#define TEGRA30_MC_DISPLAY0AB 2 +#define TEGRA30_MC_DISPLAY0B 3 +#define TEGRA30_MC_DISPLAY0BB 4 +#define TEGRA30_MC_DISPLAY0C 5 +#define TEGRA30_MC_DISPLAY0CB 6 +#define TEGRA30_MC_DISPLAY1B 7 +#define TEGRA30_MC_DISPLAY1BB 8 +#define TEGRA30_MC_EPPUP 9 +#define TEGRA30_MC_G2PR 10 +#define TEGRA30_MC_G2SR 11 +#define TEGRA30_MC_MPEUNIFBR 12 +#define TEGRA30_MC_VIRUV 13 +#define TEGRA30_MC_AFIR 14 +#define TEGRA30_MC_AVPCARM7R 15 +#define TEGRA30_MC_DISPLAYHC 16 +#define TEGRA30_MC_DISPLAYHCB 17 +#define TEGRA30_MC_FDCDRD 18 +#define TEGRA30_MC_FDCDRD2 19 +#define TEGRA30_MC_G2DR 20 +#define TEGRA30_MC_HDAR 21 +#define TEGRA30_MC_HOST1XDMAR 22 +#define TEGRA30_MC_HOST1XR 23 +#define TEGRA30_MC_IDXSRD 24 +#define TEGRA30_MC_IDXSRD2 25 +#define TEGRA30_MC_MPE_IPRED 26 +#define TEGRA30_MC_MPEAMEMRD 27 +#define TEGRA30_MC_MPECSRD 28 +#define TEGRA30_MC_PPCSAHBDMAR 29 +#define TEGRA30_MC_PPCSAHBSLVR 30 +#define TEGRA30_MC_SATAR 31 +#define TEGRA30_MC_TEXSRD 32 +#define TEGRA30_MC_TEXSRD2 33 +#define TEGRA30_MC_VDEBSEVR 34 +#define TEGRA30_MC_VDEMBER 35 +#define TEGRA30_MC_VDEMCER 36 +#define TEGRA30_MC_VDETPER 37 +#define TEGRA30_MC_MPCORELPR 38 +#define TEGRA30_MC_MPCORER 39 +#define TEGRA30_MC_EPPU 40 +#define TEGRA30_MC_EPPV 41 +#define TEGRA30_MC_EPPY 42 +#define TEGRA30_MC_MPEUNIFBW 43 +#define TEGRA30_MC_VIWSB 44 +#define TEGRA30_MC_VIWU 45 +#define TEGRA30_MC_VIWV 46 +#define TEGRA30_MC_VIWY 47 +#define TEGRA30_MC_G2DW 48 +#define TEGRA30_MC_AFIW 49 +#define TEGRA30_MC_AVPCARM7W 50 +#define TEGRA30_MC_FDCDWR 51 +#define TEGRA30_MC_FDCDWR2 52 +#define TEGRA30_MC_HDAW 53 +#define TEGRA30_MC_HOST1XW 54 +#define TEGRA30_MC_ISPW 55 +#define TEGRA30_MC_MPCORELPW 56 +#define TEGRA30_MC_MPCOREW 57 +#define TEGRA30_MC_MPECSWR 58 +#define TEGRA30_MC_PPCSAHBDMAW 59 +#define TEGRA30_MC_PPCSAHBSLVW 60 +#define TEGRA30_MC_SATAW 61 +#define TEGRA30_MC_VDEBSEVW 62 +#define TEGRA30_MC_VDEDBGW 63 +#define TEGRA30_MC_VDEMBEW 64 +#define TEGRA30_MC_VDETPMW 65 + #endif -- 2.26.0 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
next prev parent reply other threads:[~2020-06-09 13:13 UTC|newest] Thread overview: 171+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-06-09 13:13 [PATCH v4 00/37] Introduce memory interconnect for NVIDIA Tegra SoCs Dmitry Osipenko 2020-06-09 13:13 ` Dmitry Osipenko 2020-06-09 13:13 ` Dmitry Osipenko 2020-06-09 13:13 ` [PATCH v4 02/37] clk: tegra: Remove Memory Controller lock Dmitry Osipenko 2020-06-09 13:13 ` Dmitry Osipenko 2020-06-09 13:13 ` [PATCH v4 05/37] memory: tegra30-emc: Make driver modular Dmitry Osipenko 2020-06-09 13:13 ` Dmitry Osipenko 2020-06-09 13:13 ` [PATCH v4 06/37] memory: tegra124-emc: " Dmitry Osipenko 2020-06-09 13:13 ` Dmitry Osipenko 2020-06-09 13:13 ` [PATCH v4 08/37] soc/tegra: fuse: Export tegra_read_ram_code() Dmitry Osipenko 2020-06-09 13:13 ` Dmitry Osipenko 2020-06-09 13:13 ` [PATCH v4 09/37] memory: tegra20-emc: Initialize MC timings Dmitry Osipenko 2020-06-09 13:13 ` Dmitry Osipenko 2020-06-09 13:13 ` [PATCH v4 14/37] PM / devfreq: tegra20: Add error messages to tegra_devfreq_target() Dmitry Osipenko 2020-06-09 13:13 ` Dmitry Osipenko [not found] ` <20200609131404.17523-15-digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> 2020-07-02 1:12 ` Chanwoo Choi 2020-07-02 1:12 ` Chanwoo Choi 2020-07-02 1:12 ` Chanwoo Choi 2020-06-09 13:13 ` [PATCH v4 15/37] PM / devfreq: tegra30: " Dmitry Osipenko 2020-06-09 13:13 ` Dmitry Osipenko [not found] ` <20200609131404.17523-16-digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> 2020-07-02 1:12 ` Chanwoo Choi 2020-07-02 1:12 ` Chanwoo Choi 2020-07-02 1:12 ` Chanwoo Choi 2020-06-09 13:13 ` [PATCH v4 16/37] PM / devfreq: tegra20: Adjust clocks conversion ratio and polling interval Dmitry Osipenko 2020-06-09 13:13 ` Dmitry Osipenko [not found] ` <20200609131404.17523-17-digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> 2020-07-02 1:37 ` Chanwoo Choi 2020-07-02 1:37 ` Chanwoo Choi 2020-07-02 1:37 ` Chanwoo Choi 2020-06-09 13:13 ` [PATCH v4 19/37] dt-bindings: memory: tegra20: emc: Document new interconnect property Dmitry Osipenko 2020-06-09 13:13 ` Dmitry Osipenko [not found] ` <20200609131404.17523-1-digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> 2020-06-09 13:13 ` [PATCH v4 01/37] clk: Export clk_hw_reparent() Dmitry Osipenko 2020-06-09 13:13 ` Dmitry Osipenko 2020-06-09 13:13 ` Dmitry Osipenko 2020-06-09 13:13 ` [PATCH v4 03/37] clk: tegra: Export Tegra20 EMC kernel symbols Dmitry Osipenko 2020-06-09 13:13 ` Dmitry Osipenko 2020-06-09 13:13 ` Dmitry Osipenko 2020-06-09 13:13 ` [PATCH v4 04/37] memory: tegra20-emc: Make driver modular Dmitry Osipenko 2020-06-09 13:13 ` Dmitry Osipenko 2020-06-09 13:13 ` Dmitry Osipenko 2020-06-09 13:13 ` [PATCH v4 07/37] memory: tegra124-emc: Use devm_platform_ioremap_resource Dmitry Osipenko 2020-06-09 13:13 ` Dmitry Osipenko 2020-06-09 13:13 ` Dmitry Osipenko 2020-06-09 13:13 ` [PATCH v4 10/37] PM / devfreq: tegra20: Silence deferred probe error Dmitry Osipenko 2020-06-09 13:13 ` Dmitry Osipenko 2020-06-09 13:13 ` Dmitry Osipenko [not found] ` <20200609131404.17523-11-digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> 2020-07-02 0:56 ` Chanwoo Choi 2020-07-02 0:56 ` Chanwoo Choi 2020-07-02 0:56 ` Chanwoo Choi [not found] ` <14271aed-5fb6-14e1-3fe9-ef8d0c5013c4-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org> 2020-07-02 1:35 ` Chanwoo Choi 2020-07-02 1:35 ` Chanwoo Choi 2020-07-02 1:35 ` Chanwoo Choi 2020-06-09 13:13 ` [PATCH v4 11/37] PM / devfreq: tegra30: " Dmitry Osipenko 2020-06-09 13:13 ` Dmitry Osipenko 2020-06-09 13:13 ` Dmitry Osipenko [not found] ` <20200609131404.17523-12-digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> 2020-07-02 0:59 ` Chanwoo Choi 2020-07-02 0:59 ` Chanwoo Choi 2020-07-02 0:59 ` Chanwoo Choi [not found] ` <136b430d-2097-7b2b-d7dd-b438deee8f5d-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org> 2020-07-02 1:20 ` Dmitry Osipenko 2020-07-02 1:20 ` Dmitry Osipenko 2020-07-02 1:20 ` Dmitry Osipenko 2020-07-02 1:34 ` Chanwoo Choi 2020-07-02 1:34 ` Chanwoo Choi [not found] ` <8e941321-5da6-e9e7-6a4e-8c0477911ebd-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org> 2020-07-02 1:25 ` Dmitry Osipenko 2020-07-02 1:25 ` Dmitry Osipenko 2020-07-02 1:25 ` Dmitry Osipenko 2020-06-09 13:13 ` [PATCH v4 12/37] PM / devfreq: tegra20: Use MC timings for building OPP table Dmitry Osipenko 2020-06-09 13:13 ` Dmitry Osipenko 2020-06-09 13:13 ` Dmitry Osipenko [not found] ` <20200609131404.17523-13-digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> 2020-07-02 4:18 ` Chanwoo Choi 2020-07-02 4:18 ` Chanwoo Choi 2020-07-02 4:18 ` Chanwoo Choi [not found] ` <4ea7fe00-7676-3186-8222-6e0d0eb8ed1f-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org> 2020-07-02 5:07 ` Dmitry Osipenko 2020-07-02 5:07 ` Dmitry Osipenko 2020-07-02 5:07 ` Dmitry Osipenko [not found] ` <4b22d3ee-f303-d81d-e261-187d4a46e749-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> 2020-07-02 5:30 ` Chanwoo Choi 2020-07-02 5:30 ` Chanwoo Choi 2020-07-02 5:30 ` Chanwoo Choi [not found] ` <2069fb51-f043-795d-7768-0024fc9a9f4e-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org> 2020-07-02 5:43 ` Dmitry Osipenko 2020-07-02 5:43 ` Dmitry Osipenko 2020-07-02 5:43 ` Dmitry Osipenko [not found] ` <7988b6cf-e60c-7e5c-ffc3-8075c20af3d3-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> 2020-07-02 5:53 ` Dmitry Osipenko 2020-07-02 5:53 ` Dmitry Osipenko 2020-07-02 5:53 ` Dmitry Osipenko 2020-06-09 13:13 ` [PATCH v4 13/37] PM / devfreq: tegra30: " Dmitry Osipenko 2020-06-09 13:13 ` Dmitry Osipenko 2020-06-09 13:13 ` Dmitry Osipenko 2020-06-09 13:13 ` [PATCH v4 17/37] PM / devfreq: tegra20: Relax Kconfig dependency Dmitry Osipenko 2020-06-09 13:13 ` Dmitry Osipenko 2020-06-09 13:13 ` Dmitry Osipenko [not found] ` <20200609131404.17523-18-digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> 2020-07-02 2:10 ` Chanwoo Choi 2020-07-02 2:10 ` Chanwoo Choi 2020-07-02 2:10 ` Chanwoo Choi 2020-06-09 13:13 ` [PATCH v4 18/37] dt-bindings: memory: tegra20: mc: Document new interconnect property Dmitry Osipenko 2020-06-09 13:13 ` Dmitry Osipenko 2020-06-09 13:13 ` Dmitry Osipenko 2020-06-09 13:13 ` [PATCH v4 20/37] dt-bindings: memory: tegra30: " Dmitry Osipenko 2020-06-09 13:13 ` Dmitry Osipenko 2020-06-09 13:13 ` Dmitry Osipenko 2020-06-09 13:13 ` [PATCH v4 21/37] dt-bindings: memory: tegra30: emc: " Dmitry Osipenko 2020-06-09 13:13 ` Dmitry Osipenko 2020-06-09 13:13 ` Dmitry Osipenko 2020-06-09 13:13 ` [PATCH v4 22/37] dt-bindings: host1x: Document new interconnect properties Dmitry Osipenko 2020-06-09 13:13 ` Dmitry Osipenko 2020-06-09 13:13 ` Dmitry Osipenko [not found] ` <20200609131404.17523-23-digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> 2020-06-17 21:37 ` Rob Herring 2020-06-17 21:37 ` Rob Herring 2020-06-17 21:37 ` Rob Herring 2020-06-17 21:44 ` Dmitry Osipenko 2020-06-17 21:44 ` Dmitry Osipenko 2020-06-17 21:44 ` Dmitry Osipenko [not found] ` <5303317a-2cb6-d7a8-361a-30867fc6eab7-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> 2020-06-17 21:48 ` Dmitry Osipenko 2020-06-17 21:48 ` Dmitry Osipenko 2020-06-17 21:48 ` Dmitry Osipenko 2020-06-09 13:13 ` [PATCH v4 23/37] dt-bindings: memory: tegra20: Add memory client IDs Dmitry Osipenko 2020-06-09 13:13 ` Dmitry Osipenko 2020-06-09 13:13 ` Dmitry Osipenko 2020-06-09 13:13 ` [PATCH v4 25/37] ARM: tegra: Add interconnect properties to Tegra20 device-tree Dmitry Osipenko 2020-06-09 13:13 ` Dmitry Osipenko 2020-06-09 13:13 ` Dmitry Osipenko 2020-06-09 13:13 ` [PATCH v4 26/37] ARM: tegra: Add interconnect properties to Tegra30 device-tree Dmitry Osipenko 2020-06-09 13:13 ` Dmitry Osipenko 2020-06-09 13:13 ` Dmitry Osipenko 2020-06-09 13:13 ` [PATCH v4 27/37] interconnect: Relax requirement in of_icc_get_from_provider() Dmitry Osipenko 2020-06-09 13:13 ` Dmitry Osipenko 2020-06-09 13:13 ` Dmitry Osipenko [not found] ` <20200609131404.17523-28-digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> 2020-07-01 17:10 ` Georgi Djakov 2020-07-01 17:10 ` Georgi Djakov 2020-07-01 17:10 ` Georgi Djakov [not found] ` <3b410ea3-26d3-6f7a-213c-40dbabbde8d1-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> 2020-07-01 23:41 ` Dmitry Osipenko 2020-07-01 23:41 ` Dmitry Osipenko 2020-07-01 23:41 ` Dmitry Osipenko 2020-06-09 13:13 ` [PATCH v4 28/37] memory: tegra: Register as interconnect provider Dmitry Osipenko 2020-06-09 13:13 ` Dmitry Osipenko 2020-06-09 13:13 ` Dmitry Osipenko [not found] ` <20200609131404.17523-29-digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> 2020-07-01 17:12 ` Georgi Djakov 2020-07-01 17:12 ` Georgi Djakov 2020-07-01 17:12 ` Georgi Djakov [not found] ` <aec831a6-a7ad-6bcc-4e15-c44582f7568e-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> 2020-07-01 23:36 ` Dmitry Osipenko 2020-07-01 23:36 ` Dmitry Osipenko 2020-07-01 23:36 ` Dmitry Osipenko [not found] ` <82d27a47-f189-6609-a584-c9ca1b35a76c-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> 2020-07-02 12:36 ` Georgi Djakov 2020-07-02 12:36 ` Georgi Djakov 2020-07-02 12:36 ` Georgi Djakov 2020-07-03 8:41 ` Dmitry Osipenko 2020-07-03 8:41 ` Dmitry Osipenko 2020-06-09 13:13 ` [PATCH v4 30/37] memory: tegra20-emc: Continue probing if timings are missing in device-tree Dmitry Osipenko 2020-06-09 13:13 ` Dmitry Osipenko 2020-06-09 13:13 ` Dmitry Osipenko 2020-06-09 13:13 ` [PATCH v4 31/37] memory: tegra20-emc: Register as interconnect provider Dmitry Osipenko 2020-06-09 13:13 ` Dmitry Osipenko 2020-06-09 13:13 ` Dmitry Osipenko 2020-06-09 13:13 ` [PATCH v4 32/37] memory: tegra20-emc: Create tegra20-devfreq device Dmitry Osipenko 2020-06-09 13:13 ` Dmitry Osipenko 2020-06-09 13:13 ` Dmitry Osipenko 2020-06-09 13:14 ` [PATCH v4 33/37] memory: tegra30-emc: Continue probing if timings are missing in device-tree Dmitry Osipenko 2020-06-09 13:14 ` Dmitry Osipenko 2020-06-09 13:14 ` Dmitry Osipenko 2020-06-09 13:14 ` [PATCH v4 36/37] drm/tegra: dc: Tune up high priority request controls for Tegra20 Dmitry Osipenko 2020-06-09 13:14 ` Dmitry Osipenko 2020-06-09 13:14 ` Dmitry Osipenko 2020-06-09 13:14 ` [PATCH v4 37/37] drm/tegra: dc: Extend debug stats with total number of events Dmitry Osipenko 2020-06-09 13:14 ` Dmitry Osipenko 2020-06-09 13:14 ` Dmitry Osipenko 2020-06-09 13:13 ` Dmitry Osipenko [this message] 2020-06-09 13:13 ` [PATCH v4 24/37] dt-bindings: memory: tegra30: Add memory client IDs Dmitry Osipenko 2020-06-09 13:13 ` [PATCH v4 29/37] memory: tegra20-emc: Use devm_platform_ioremap_resource Dmitry Osipenko 2020-06-09 13:13 ` Dmitry Osipenko 2020-06-09 13:14 ` [PATCH v4 34/37] memory: tegra30-emc: Register as interconnect provider Dmitry Osipenko 2020-06-09 13:14 ` Dmitry Osipenko 2020-06-09 13:14 ` [PATCH v4 35/37] drm/tegra: dc: Support memory bandwidth management Dmitry Osipenko 2020-06-09 13:14 ` Dmitry Osipenko
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