From: "Uwe Kleine-König" <u.kleine-koenig@pengutronix.de>
To: Hans de Goede <hdegoede@redhat.com>
Cc: "Andy Shevchenko" <andriy.shevchenko@linux.intel.com>,
"Thierry Reding" <thierry.reding@gmail.com>,
"Jani Nikula" <jani.nikula@linux.intel.com>,
"Joonas Lahtinen" <joonas.lahtinen@linux.intel.com>,
"Ville Syrjälä" <ville.syrjala@linux.intel.com>,
"Rafael J . Wysocki" <rjw@rjwysocki.net>,
"Len Brown" <lenb@kernel.org>,
linux-pwm@vger.kernel.org,
intel-gfx <intel-gfx@lists.freedesktop.org>,
dri-devel@lists.freedesktop.org,
"Mika Westerberg" <mika.westerberg@linux.intel.com>,
linux-acpi@vger.kernel.org
Subject: Re: [PATCH v2 03/15] pwm: lpss: Add range limit check for the base_unit register value
Date: Fri, 12 Jun 2020 00:12:42 +0200 [thread overview]
Message-ID: <20200611221242.3bjqvnhcwwxaocxy@taurus.defre.kleine-koenig.org> (raw)
In-Reply-To: <90769dc0-3174-195b-34e0-ef4bb9d9b982@redhat.com>
[-- Attachment #1: Type: text/plain, Size: 1598 bytes --]
On Mon, Jun 08, 2020 at 01:07:12PM +0200, Hans de Goede wrote:
> Hi,
>
> On 6/8/20 5:50 AM, Andy Shevchenko wrote:
> > On Sun, Jun 07, 2020 at 08:18:28PM +0200, Hans de Goede wrote:
> > > When the user requests a high enough period ns value, then the
> > > calculations in pwm_lpss_prepare() might result in a base_unit value of 0.
> > >
> > > But according to the data-sheet the way the PWM controller works is that
> > > each input clock-cycle the base_unit gets added to a N bit counter and
> > > that counter overflowing determines the PWM output frequency. Adding 0
> > > to the counter is a no-op. The data-sheet even explicitly states that
> > > writing 0 to the base_unit bits will result in the PWM outputting a
> > > continuous 0 signal.
> >
> > So, and why it's a problem?
>
> Lets sya the user requests a PWM output frequency of 100Hz on Cherry Trail
> which has a 19200000 Hz clock this will result in 100 * 65536 / 19200000 =
> 0.3 -> 0 as base-unit value. So instead of getting 100 Hz the user will
> now get a pin which is always outputting low.
I didn't follow the complete discussion but note that the general rule
is:
round period down to the next possible implementable period
round duty_cycle down to the next possible implementable duty_cycle
so if a small enough period (and so a small duty_cycle) is requested it
is expected that duty_cycle will be zero.
Best regards
Uwe
--
Pengutronix e.K. | Uwe Kleine-König |
Industrial Linux Solutions | https://www.pengutronix.de/ |
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
WARNING: multiple messages have this Message-ID (diff)
From: "Uwe Kleine-König" <u.kleine-koenig@pengutronix.de>
To: Hans de Goede <hdegoede@redhat.com>
Cc: linux-pwm@vger.kernel.org,
intel-gfx <intel-gfx@lists.freedesktop.org>,
"Rafael J . Wysocki" <rjw@rjwysocki.net>,
linux-acpi@vger.kernel.org,
Thierry Reding <thierry.reding@gmail.com>,
dri-devel@lists.freedesktop.org,
Andy Shevchenko <andriy.shevchenko@linux.intel.com>,
Mika Westerberg <mika.westerberg@linux.intel.com>,
Len Brown <lenb@kernel.org>
Subject: Re: [PATCH v2 03/15] pwm: lpss: Add range limit check for the base_unit register value
Date: Fri, 12 Jun 2020 00:12:42 +0200 [thread overview]
Message-ID: <20200611221242.3bjqvnhcwwxaocxy@taurus.defre.kleine-koenig.org> (raw)
In-Reply-To: <90769dc0-3174-195b-34e0-ef4bb9d9b982@redhat.com>
[-- Attachment #1.1: Type: text/plain, Size: 1598 bytes --]
On Mon, Jun 08, 2020 at 01:07:12PM +0200, Hans de Goede wrote:
> Hi,
>
> On 6/8/20 5:50 AM, Andy Shevchenko wrote:
> > On Sun, Jun 07, 2020 at 08:18:28PM +0200, Hans de Goede wrote:
> > > When the user requests a high enough period ns value, then the
> > > calculations in pwm_lpss_prepare() might result in a base_unit value of 0.
> > >
> > > But according to the data-sheet the way the PWM controller works is that
> > > each input clock-cycle the base_unit gets added to a N bit counter and
> > > that counter overflowing determines the PWM output frequency. Adding 0
> > > to the counter is a no-op. The data-sheet even explicitly states that
> > > writing 0 to the base_unit bits will result in the PWM outputting a
> > > continuous 0 signal.
> >
> > So, and why it's a problem?
>
> Lets sya the user requests a PWM output frequency of 100Hz on Cherry Trail
> which has a 19200000 Hz clock this will result in 100 * 65536 / 19200000 =
> 0.3 -> 0 as base-unit value. So instead of getting 100 Hz the user will
> now get a pin which is always outputting low.
I didn't follow the complete discussion but note that the general rule
is:
round period down to the next possible implementable period
round duty_cycle down to the next possible implementable duty_cycle
so if a small enough period (and so a small duty_cycle) is requested it
is expected that duty_cycle will be zero.
Best regards
Uwe
--
Pengutronix e.K. | Uwe Kleine-König |
Industrial Linux Solutions | https://www.pengutronix.de/ |
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
WARNING: multiple messages have this Message-ID (diff)
From: "Uwe Kleine-König" <u.kleine-koenig@pengutronix.de>
To: Hans de Goede <hdegoede@redhat.com>
Cc: linux-pwm@vger.kernel.org,
intel-gfx <intel-gfx@lists.freedesktop.org>,
"Rafael J . Wysocki" <rjw@rjwysocki.net>,
linux-acpi@vger.kernel.org, dri-devel@lists.freedesktop.org,
Andy Shevchenko <andriy.shevchenko@linux.intel.com>,
Mika Westerberg <mika.westerberg@linux.intel.com>,
Len Brown <lenb@kernel.org>
Subject: Re: [Intel-gfx] [PATCH v2 03/15] pwm: lpss: Add range limit check for the base_unit register value
Date: Fri, 12 Jun 2020 00:12:42 +0200 [thread overview]
Message-ID: <20200611221242.3bjqvnhcwwxaocxy@taurus.defre.kleine-koenig.org> (raw)
In-Reply-To: <90769dc0-3174-195b-34e0-ef4bb9d9b982@redhat.com>
[-- Attachment #1.1: Type: text/plain, Size: 1598 bytes --]
On Mon, Jun 08, 2020 at 01:07:12PM +0200, Hans de Goede wrote:
> Hi,
>
> On 6/8/20 5:50 AM, Andy Shevchenko wrote:
> > On Sun, Jun 07, 2020 at 08:18:28PM +0200, Hans de Goede wrote:
> > > When the user requests a high enough period ns value, then the
> > > calculations in pwm_lpss_prepare() might result in a base_unit value of 0.
> > >
> > > But according to the data-sheet the way the PWM controller works is that
> > > each input clock-cycle the base_unit gets added to a N bit counter and
> > > that counter overflowing determines the PWM output frequency. Adding 0
> > > to the counter is a no-op. The data-sheet even explicitly states that
> > > writing 0 to the base_unit bits will result in the PWM outputting a
> > > continuous 0 signal.
> >
> > So, and why it's a problem?
>
> Lets sya the user requests a PWM output frequency of 100Hz on Cherry Trail
> which has a 19200000 Hz clock this will result in 100 * 65536 / 19200000 =
> 0.3 -> 0 as base-unit value. So instead of getting 100 Hz the user will
> now get a pin which is always outputting low.
I didn't follow the complete discussion but note that the general rule
is:
round period down to the next possible implementable period
round duty_cycle down to the next possible implementable duty_cycle
so if a small enough period (and so a small duty_cycle) is requested it
is expected that duty_cycle will be zero.
Best regards
Uwe
--
Pengutronix e.K. | Uwe Kleine-König |
Industrial Linux Solutions | https://www.pengutronix.de/ |
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2020-06-11 22:12 UTC|newest]
Thread overview: 116+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-07 18:18 [PATCH v2 00/15] pwm/i915: Convert pwm-crc and i915 driver's PWM code to use the atomic PWM API Hans de Goede
2020-06-07 18:18 ` [Intel-gfx] " Hans de Goede
2020-06-07 18:18 ` Hans de Goede
2020-06-07 18:18 ` [PATCH v2 01/15] ACPI / LPSS: Resume Cherry Trail PWM controller in no-irq phase Hans de Goede
2020-06-07 18:18 ` [Intel-gfx] " Hans de Goede
2020-06-07 18:18 ` Hans de Goede
2020-06-07 18:18 ` [PATCH v2 02/15] ACPI / LPSS: Save Cherry Trail PWM ctx registers only once (at activation) Hans de Goede
2020-06-07 18:18 ` [Intel-gfx] " Hans de Goede
2020-06-07 18:18 ` Hans de Goede
2020-06-07 18:18 ` [PATCH v2 03/15] pwm: lpss: Add range limit check for the base_unit register value Hans de Goede
2020-06-07 18:18 ` [Intel-gfx] " Hans de Goede
2020-06-07 18:18 ` Hans de Goede
2020-06-08 3:50 ` Andy Shevchenko
2020-06-08 3:50 ` [Intel-gfx] " Andy Shevchenko
2020-06-08 3:50 ` Andy Shevchenko
2020-06-08 11:07 ` Hans de Goede
2020-06-08 11:07 ` [Intel-gfx] " Hans de Goede
2020-06-08 11:07 ` Hans de Goede
2020-06-08 12:51 ` Andy Shevchenko
2020-06-08 12:51 ` [Intel-gfx] " Andy Shevchenko
2020-06-08 12:51 ` Andy Shevchenko
2020-06-08 12:51 ` Andy Shevchenko
2020-06-08 14:19 ` Hans de Goede
2020-06-08 14:19 ` [Intel-gfx] " Hans de Goede
2020-06-08 14:19 ` Hans de Goede
2020-06-11 22:12 ` Uwe Kleine-König [this message]
2020-06-11 22:12 ` [Intel-gfx] " Uwe Kleine-König
2020-06-11 22:12 ` Uwe Kleine-König
2020-06-12 11:57 ` Andy Shevchenko
2020-06-12 11:57 ` [Intel-gfx] " Andy Shevchenko
2020-06-12 11:57 ` Andy Shevchenko
2020-06-13 20:50 ` Uwe Kleine-König
2020-06-13 20:50 ` [Intel-gfx] " Uwe Kleine-König
2020-06-13 20:50 ` Uwe Kleine-König
2020-06-07 18:18 ` [PATCH v2 04/15] pwm: lpss: Fix off by one error in base_unit math in pwm_lpss_prepare() Hans de Goede
2020-06-07 18:18 ` [Intel-gfx] " Hans de Goede
2020-06-07 18:18 ` Hans de Goede
2020-06-08 3:55 ` Andy Shevchenko
2020-06-08 3:55 ` [Intel-gfx] " Andy Shevchenko
2020-06-08 3:55 ` Andy Shevchenko
2020-06-08 11:13 ` Hans de Goede
2020-06-08 11:13 ` [Intel-gfx] " Hans de Goede
2020-06-08 11:13 ` Hans de Goede
2020-06-08 11:13 ` Hans de Goede
2020-06-08 12:55 ` Andy Shevchenko
2020-06-08 12:55 ` [Intel-gfx] " Andy Shevchenko
2020-06-08 12:55 ` Andy Shevchenko
2020-06-07 18:18 ` [PATCH v2 05/15] pwm: lpss: Set SW_UPDATE bit when enabling the PWM Hans de Goede
2020-06-07 18:18 ` [Intel-gfx] " Hans de Goede
2020-06-07 18:18 ` Hans de Goede
2020-06-07 18:18 ` [PATCH v2 06/15] pwm: crc: Fix period / duty_cycle times being off by a factor of 256 Hans de Goede
2020-06-07 18:18 ` [Intel-gfx] " Hans de Goede
2020-06-07 18:18 ` Hans de Goede
2020-06-09 11:29 ` Andy Shevchenko
2020-06-09 11:29 ` [Intel-gfx] " Andy Shevchenko
2020-06-09 11:29 ` Andy Shevchenko
2020-06-09 13:45 ` Hans de Goede
2020-06-09 13:45 ` [Intel-gfx] " Hans de Goede
2020-06-09 13:45 ` Hans de Goede
2020-06-07 18:18 ` [PATCH v2 07/15] pwm: crc: Fix off-by-one error in the clock-divider calculations Hans de Goede
2020-06-07 18:18 ` [Intel-gfx] " Hans de Goede
2020-06-07 18:18 ` Hans de Goede
2020-06-07 18:18 ` [PATCH v2 08/15] pwm: crc: Fix period changes not having any effect Hans de Goede
2020-06-07 18:18 ` [Intel-gfx] " Hans de Goede
2020-06-07 18:18 ` Hans de Goede
2020-06-07 18:18 ` [PATCH v2 09/15] pwm: crc: Enable/disable PWM output on enable/disable Hans de Goede
2020-06-07 18:18 ` [Intel-gfx] " Hans de Goede
2020-06-07 18:18 ` Hans de Goede
2020-06-09 11:31 ` Andy Shevchenko
2020-06-09 11:31 ` [Intel-gfx] " Andy Shevchenko
2020-06-09 11:31 ` Andy Shevchenko
2020-06-11 22:20 ` Uwe Kleine-König
2020-06-11 22:20 ` [Intel-gfx] " Uwe Kleine-König
2020-06-11 22:20 ` Uwe Kleine-König
2020-06-12 16:59 ` Hans de Goede
2020-06-12 16:59 ` [Intel-gfx] " Hans de Goede
2020-06-12 16:59 ` Hans de Goede
2020-06-07 18:18 ` [PATCH v2 10/15] pwm: crc: Implement apply() method to support the new atomic PWM API Hans de Goede
2020-06-07 18:18 ` [Intel-gfx] " Hans de Goede
2020-06-07 18:18 ` Hans de Goede
2020-06-09 11:32 ` Andy Shevchenko
2020-06-09 11:32 ` [Intel-gfx] " Andy Shevchenko
2020-06-09 11:32 ` Andy Shevchenko
2020-06-09 13:44 ` Hans de Goede
2020-06-09 13:44 ` [Intel-gfx] " Hans de Goede
2020-06-09 13:44 ` Hans de Goede
2020-06-09 13:50 ` Andy Shevchenko
2020-06-09 13:50 ` [Intel-gfx] " Andy Shevchenko
2020-06-09 13:50 ` Andy Shevchenko
2020-06-07 18:18 ` [PATCH v2 11/15] pwm: crc: Implement get_state() method Hans de Goede
2020-06-07 18:18 ` [Intel-gfx] " Hans de Goede
2020-06-07 18:18 ` Hans de Goede
2020-06-09 11:32 ` Andy Shevchenko
2020-06-09 11:32 ` [Intel-gfx] " Andy Shevchenko
2020-06-09 11:32 ` Andy Shevchenko
2020-06-11 21:37 ` Uwe Kleine-König
2020-06-11 21:37 ` [Intel-gfx] " Uwe Kleine-König
2020-06-11 21:37 ` Uwe Kleine-König
2020-06-12 17:00 ` Hans de Goede
2020-06-12 17:00 ` [Intel-gfx] " Hans de Goede
2020-06-12 17:00 ` Hans de Goede
2020-06-07 18:18 ` [PATCH v2 12/15] drm/i915: panel: Add get_vbt_pwm_freq() helper Hans de Goede
2020-06-07 18:18 ` [Intel-gfx] " Hans de Goede
2020-06-07 18:18 ` Hans de Goede
2020-06-07 18:18 ` [PATCH v2 13/15] drm/i915: panel: Honor the VBT PWM frequency for devs with an external PWM controller Hans de Goede
2020-06-07 18:18 ` [Intel-gfx] " Hans de Goede
2020-06-07 18:18 ` Hans de Goede
2020-06-07 18:18 ` [PATCH v2 14/15] drm/i915: panel: Honor the VBT PWM min setting " Hans de Goede
2020-06-07 18:18 ` [Intel-gfx] " Hans de Goede
2020-06-07 18:18 ` Hans de Goede
2020-06-07 18:18 ` [PATCH v2 15/15] drm/i915: panel: Use atomic PWM API " Hans de Goede
2020-06-07 18:18 ` [Intel-gfx] " Hans de Goede
2020-06-07 18:18 ` Hans de Goede
2020-06-07 18:28 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for pwm/i915: Convert pwm-crc and i915 driver's PWM code to use the atomic PWM API Patchwork
2020-06-07 18:48 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-06-07 19:44 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20200611221242.3bjqvnhcwwxaocxy@taurus.defre.kleine-koenig.org \
--to=u.kleine-koenig@pengutronix.de \
--cc=andriy.shevchenko@linux.intel.com \
--cc=dri-devel@lists.freedesktop.org \
--cc=hdegoede@redhat.com \
--cc=intel-gfx@lists.freedesktop.org \
--cc=jani.nikula@linux.intel.com \
--cc=joonas.lahtinen@linux.intel.com \
--cc=lenb@kernel.org \
--cc=linux-acpi@vger.kernel.org \
--cc=linux-pwm@vger.kernel.org \
--cc=mika.westerberg@linux.intel.com \
--cc=rjw@rjwysocki.net \
--cc=thierry.reding@gmail.com \
--cc=ville.syrjala@linux.intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.