From: Chao Hao <chao.hao@mediatek.com>
To: Joerg Roedel <joro@8bytes.org>, Rob Herring <robh+dt@kernel.org>,
"Matthias Brugger" <matthias.bgg@gmail.com>
Cc: <iommu@lists.linux-foundation.org>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-mediatek@lists.infradead.org>, <wsd_upstream@mediatek.com>,
Chao Hao <chao.hao@mediatek.com>, FY Yang <fy.yang@mediatek.com>,
Yong Wu <yong.wu@mediatek.com>, TH Yang <th.yang@mediatek.com>
Subject: [PATCH v6 04/10] iommu/mediatek: Setting MISC_CTRL register
Date: Fri, 3 Jul 2020 12:41:21 +0800 [thread overview]
Message-ID: <20200703044127.27438-5-chao.hao@mediatek.com> (raw)
In-Reply-To: <20200703044127.27438-1-chao.hao@mediatek.com>
Add F_MMU_IN_ORDER_WR_EN_MASK and F_MMU_STANDARD_AXI_MODE_EN_MASK
definitions in MISC_CTRL register.
F_MMU_STANDARD_AXI_MODE_EN_MASK:
If we set F_MMU_STANDARD_AXI_MODE_EN_MASK (bit[3][19] = 0, not follow
standard AXI protocol), the iommu will priorize sending of urgent read
command over a normal read command. This improves the performance.
F_MMU_IN_ORDER_WR_EN_MASK:
If we set F_MMU_IN_ORDER_WR_EN_MASK (bit[1][17] = 0, out-of-order write),
the iommu will re-order write commands and send the write commands with
higher priority. Otherwise the sending of write commands will be done in
order. The feature is controlled by OUT_ORDER_WR_EN platform data flag.
Cc: Matthias Brugger <matthias.bgg@gmail.com>
Suggested-by: Yong Wu <yong.wu@mediatek.com>
Signed-off-by: Chao Hao <chao.hao@mediatek.com>
---
drivers/iommu/mtk_iommu.c | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index 40ca564d97af..219d7aa6f059 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -42,6 +42,9 @@
#define F_INVLD_EN1 BIT(1)
#define REG_MMU_MISC_CTRL 0x048
+#define F_MMU_IN_ORDER_WR_EN_MASK (BIT(1) | BIT(17))
+#define F_MMU_STANDARD_AXI_MODE_MASK (BIT(3) | BIT(19))
+
#define REG_MMU_DCM_DIS 0x050
#define REG_MMU_CTRL_REG 0x110
@@ -105,6 +108,7 @@
#define HAS_BCLK BIT(1)
#define HAS_VLD_PA_RNG BIT(2)
#define RESET_AXI BIT(3)
+#define OUT_ORDER_WR_EN BIT(4)
#define MTK_IOMMU_HAS_FLAG(pdata, _x) \
((((pdata)->flags) & (_x)) == (_x))
@@ -585,8 +589,14 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
if (MTK_IOMMU_HAS_FLAG(data->plat_data, RESET_AXI)) {
/* The register is called STANDARD_AXI_MODE in this case */
- writel_relaxed(0, data->base + REG_MMU_MISC_CTRL);
+ regval = 0;
+ } else {
+ regval = readl_relaxed(data->base + REG_MMU_MISC_CTRL);
+ regval &= ~F_MMU_STANDARD_AXI_MODE_MASK;
+ if (MTK_IOMMU_HAS_FLAG(data->plat_data, OUT_ORDER_WR_EN))
+ regval &= ~F_MMU_IN_ORDER_WR_EN_MASK;
}
+ writel_relaxed(regval, data->base + REG_MMU_MISC_CTRL);
if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0,
dev_name(data->dev), (void *)data)) {
--
2.18.0
WARNING: multiple messages have this Message-ID (diff)
From: Chao Hao <chao.hao@mediatek.com>
To: Joerg Roedel <joro@8bytes.org>, Rob Herring <robh+dt@kernel.org>,
"Matthias Brugger" <matthias.bgg@gmail.com>
Cc: devicetree@vger.kernel.org, FY Yang <fy.yang@mediatek.com>,
wsd_upstream@mediatek.com, linux-kernel@vger.kernel.org,
Chao Hao <chao.hao@mediatek.com>,
iommu@lists.linux-foundation.org, TH Yang <th.yang@mediatek.com>,
linux-mediatek@lists.infradead.org,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH v6 04/10] iommu/mediatek: Setting MISC_CTRL register
Date: Fri, 3 Jul 2020 12:41:21 +0800 [thread overview]
Message-ID: <20200703044127.27438-5-chao.hao@mediatek.com> (raw)
In-Reply-To: <20200703044127.27438-1-chao.hao@mediatek.com>
Add F_MMU_IN_ORDER_WR_EN_MASK and F_MMU_STANDARD_AXI_MODE_EN_MASK
definitions in MISC_CTRL register.
F_MMU_STANDARD_AXI_MODE_EN_MASK:
If we set F_MMU_STANDARD_AXI_MODE_EN_MASK (bit[3][19] = 0, not follow
standard AXI protocol), the iommu will priorize sending of urgent read
command over a normal read command. This improves the performance.
F_MMU_IN_ORDER_WR_EN_MASK:
If we set F_MMU_IN_ORDER_WR_EN_MASK (bit[1][17] = 0, out-of-order write),
the iommu will re-order write commands and send the write commands with
higher priority. Otherwise the sending of write commands will be done in
order. The feature is controlled by OUT_ORDER_WR_EN platform data flag.
Cc: Matthias Brugger <matthias.bgg@gmail.com>
Suggested-by: Yong Wu <yong.wu@mediatek.com>
Signed-off-by: Chao Hao <chao.hao@mediatek.com>
---
drivers/iommu/mtk_iommu.c | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index 40ca564d97af..219d7aa6f059 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -42,6 +42,9 @@
#define F_INVLD_EN1 BIT(1)
#define REG_MMU_MISC_CTRL 0x048
+#define F_MMU_IN_ORDER_WR_EN_MASK (BIT(1) | BIT(17))
+#define F_MMU_STANDARD_AXI_MODE_MASK (BIT(3) | BIT(19))
+
#define REG_MMU_DCM_DIS 0x050
#define REG_MMU_CTRL_REG 0x110
@@ -105,6 +108,7 @@
#define HAS_BCLK BIT(1)
#define HAS_VLD_PA_RNG BIT(2)
#define RESET_AXI BIT(3)
+#define OUT_ORDER_WR_EN BIT(4)
#define MTK_IOMMU_HAS_FLAG(pdata, _x) \
((((pdata)->flags) & (_x)) == (_x))
@@ -585,8 +589,14 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
if (MTK_IOMMU_HAS_FLAG(data->plat_data, RESET_AXI)) {
/* The register is called STANDARD_AXI_MODE in this case */
- writel_relaxed(0, data->base + REG_MMU_MISC_CTRL);
+ regval = 0;
+ } else {
+ regval = readl_relaxed(data->base + REG_MMU_MISC_CTRL);
+ regval &= ~F_MMU_STANDARD_AXI_MODE_MASK;
+ if (MTK_IOMMU_HAS_FLAG(data->plat_data, OUT_ORDER_WR_EN))
+ regval &= ~F_MMU_IN_ORDER_WR_EN_MASK;
}
+ writel_relaxed(regval, data->base + REG_MMU_MISC_CTRL);
if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0,
dev_name(data->dev), (void *)data)) {
--
2.18.0
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
WARNING: multiple messages have this Message-ID (diff)
From: Chao Hao <chao.hao@mediatek.com>
To: Joerg Roedel <joro@8bytes.org>, Rob Herring <robh+dt@kernel.org>,
"Matthias Brugger" <matthias.bgg@gmail.com>
Cc: devicetree@vger.kernel.org, FY Yang <fy.yang@mediatek.com>,
wsd_upstream@mediatek.com, linux-kernel@vger.kernel.org,
Chao Hao <chao.hao@mediatek.com>,
iommu@lists.linux-foundation.org, TH Yang <th.yang@mediatek.com>,
linux-mediatek@lists.infradead.org,
Yong Wu <yong.wu@mediatek.com>,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH v6 04/10] iommu/mediatek: Setting MISC_CTRL register
Date: Fri, 3 Jul 2020 12:41:21 +0800 [thread overview]
Message-ID: <20200703044127.27438-5-chao.hao@mediatek.com> (raw)
In-Reply-To: <20200703044127.27438-1-chao.hao@mediatek.com>
Add F_MMU_IN_ORDER_WR_EN_MASK and F_MMU_STANDARD_AXI_MODE_EN_MASK
definitions in MISC_CTRL register.
F_MMU_STANDARD_AXI_MODE_EN_MASK:
If we set F_MMU_STANDARD_AXI_MODE_EN_MASK (bit[3][19] = 0, not follow
standard AXI protocol), the iommu will priorize sending of urgent read
command over a normal read command. This improves the performance.
F_MMU_IN_ORDER_WR_EN_MASK:
If we set F_MMU_IN_ORDER_WR_EN_MASK (bit[1][17] = 0, out-of-order write),
the iommu will re-order write commands and send the write commands with
higher priority. Otherwise the sending of write commands will be done in
order. The feature is controlled by OUT_ORDER_WR_EN platform data flag.
Cc: Matthias Brugger <matthias.bgg@gmail.com>
Suggested-by: Yong Wu <yong.wu@mediatek.com>
Signed-off-by: Chao Hao <chao.hao@mediatek.com>
---
drivers/iommu/mtk_iommu.c | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index 40ca564d97af..219d7aa6f059 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -42,6 +42,9 @@
#define F_INVLD_EN1 BIT(1)
#define REG_MMU_MISC_CTRL 0x048
+#define F_MMU_IN_ORDER_WR_EN_MASK (BIT(1) | BIT(17))
+#define F_MMU_STANDARD_AXI_MODE_MASK (BIT(3) | BIT(19))
+
#define REG_MMU_DCM_DIS 0x050
#define REG_MMU_CTRL_REG 0x110
@@ -105,6 +108,7 @@
#define HAS_BCLK BIT(1)
#define HAS_VLD_PA_RNG BIT(2)
#define RESET_AXI BIT(3)
+#define OUT_ORDER_WR_EN BIT(4)
#define MTK_IOMMU_HAS_FLAG(pdata, _x) \
((((pdata)->flags) & (_x)) == (_x))
@@ -585,8 +589,14 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
if (MTK_IOMMU_HAS_FLAG(data->plat_data, RESET_AXI)) {
/* The register is called STANDARD_AXI_MODE in this case */
- writel_relaxed(0, data->base + REG_MMU_MISC_CTRL);
+ regval = 0;
+ } else {
+ regval = readl_relaxed(data->base + REG_MMU_MISC_CTRL);
+ regval &= ~F_MMU_STANDARD_AXI_MODE_MASK;
+ if (MTK_IOMMU_HAS_FLAG(data->plat_data, OUT_ORDER_WR_EN))
+ regval &= ~F_MMU_IN_ORDER_WR_EN_MASK;
}
+ writel_relaxed(regval, data->base + REG_MMU_MISC_CTRL);
if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0,
dev_name(data->dev), (void *)data)) {
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
WARNING: multiple messages have this Message-ID (diff)
From: Chao Hao <chao.hao@mediatek.com>
To: Joerg Roedel <joro@8bytes.org>, Rob Herring <robh+dt@kernel.org>,
"Matthias Brugger" <matthias.bgg@gmail.com>
Cc: devicetree@vger.kernel.org, FY Yang <fy.yang@mediatek.com>,
wsd_upstream@mediatek.com, linux-kernel@vger.kernel.org,
Chao Hao <chao.hao@mediatek.com>,
iommu@lists.linux-foundation.org, TH Yang <th.yang@mediatek.com>,
linux-mediatek@lists.infradead.org,
Yong Wu <yong.wu@mediatek.com>,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH v6 04/10] iommu/mediatek: Setting MISC_CTRL register
Date: Fri, 3 Jul 2020 12:41:21 +0800 [thread overview]
Message-ID: <20200703044127.27438-5-chao.hao@mediatek.com> (raw)
In-Reply-To: <20200703044127.27438-1-chao.hao@mediatek.com>
Add F_MMU_IN_ORDER_WR_EN_MASK and F_MMU_STANDARD_AXI_MODE_EN_MASK
definitions in MISC_CTRL register.
F_MMU_STANDARD_AXI_MODE_EN_MASK:
If we set F_MMU_STANDARD_AXI_MODE_EN_MASK (bit[3][19] = 0, not follow
standard AXI protocol), the iommu will priorize sending of urgent read
command over a normal read command. This improves the performance.
F_MMU_IN_ORDER_WR_EN_MASK:
If we set F_MMU_IN_ORDER_WR_EN_MASK (bit[1][17] = 0, out-of-order write),
the iommu will re-order write commands and send the write commands with
higher priority. Otherwise the sending of write commands will be done in
order. The feature is controlled by OUT_ORDER_WR_EN platform data flag.
Cc: Matthias Brugger <matthias.bgg@gmail.com>
Suggested-by: Yong Wu <yong.wu@mediatek.com>
Signed-off-by: Chao Hao <chao.hao@mediatek.com>
---
drivers/iommu/mtk_iommu.c | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index 40ca564d97af..219d7aa6f059 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -42,6 +42,9 @@
#define F_INVLD_EN1 BIT(1)
#define REG_MMU_MISC_CTRL 0x048
+#define F_MMU_IN_ORDER_WR_EN_MASK (BIT(1) | BIT(17))
+#define F_MMU_STANDARD_AXI_MODE_MASK (BIT(3) | BIT(19))
+
#define REG_MMU_DCM_DIS 0x050
#define REG_MMU_CTRL_REG 0x110
@@ -105,6 +108,7 @@
#define HAS_BCLK BIT(1)
#define HAS_VLD_PA_RNG BIT(2)
#define RESET_AXI BIT(3)
+#define OUT_ORDER_WR_EN BIT(4)
#define MTK_IOMMU_HAS_FLAG(pdata, _x) \
((((pdata)->flags) & (_x)) == (_x))
@@ -585,8 +589,14 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
if (MTK_IOMMU_HAS_FLAG(data->plat_data, RESET_AXI)) {
/* The register is called STANDARD_AXI_MODE in this case */
- writel_relaxed(0, data->base + REG_MMU_MISC_CTRL);
+ regval = 0;
+ } else {
+ regval = readl_relaxed(data->base + REG_MMU_MISC_CTRL);
+ regval &= ~F_MMU_STANDARD_AXI_MODE_MASK;
+ if (MTK_IOMMU_HAS_FLAG(data->plat_data, OUT_ORDER_WR_EN))
+ regval &= ~F_MMU_IN_ORDER_WR_EN_MASK;
}
+ writel_relaxed(regval, data->base + REG_MMU_MISC_CTRL);
if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0,
dev_name(data->dev), (void *)data)) {
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-07-03 4:43 UTC|newest]
Thread overview: 84+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-03 4:41 [PATCH v6 00/10] MT6779 IOMMU SUPPORT Chao Hao
2020-07-03 4:41 ` Chao Hao
2020-07-03 4:41 ` Chao Hao
2020-07-03 4:41 ` Chao Hao
2020-07-03 4:41 ` [PATCH v6 01/10] dt-bindings: mediatek: Add bindings for MT6779 Chao Hao
2020-07-03 4:41 ` Chao Hao
2020-07-03 4:41 ` Chao Hao
2020-07-03 4:41 ` Chao Hao
2020-07-03 4:41 ` [PATCH v6 02/10] iommu/mediatek: Rename the register STANDARD_AXI_MODE(0x48) to MISC_CTRL Chao Hao
2020-07-03 4:41 ` Chao Hao
2020-07-03 4:41 ` Chao Hao
2020-07-03 4:41 ` Chao Hao
2020-07-03 4:41 ` [PATCH v6 03/10] iommu/mediatek: Use a u32 flags to describe different HW features Chao Hao
2020-07-03 4:41 ` Chao Hao
2020-07-03 4:41 ` Chao Hao
2020-07-03 4:41 ` Chao Hao
2020-07-04 1:16 ` Yingjoe Chen
2020-07-04 1:16 ` Yingjoe Chen
2020-07-04 1:16 ` Yingjoe Chen
2020-07-04 1:16 ` Yingjoe Chen
2020-07-06 15:17 ` Matthias Brugger
2020-07-06 15:17 ` Matthias Brugger
2020-07-06 15:17 ` Matthias Brugger
2020-07-06 15:17 ` Matthias Brugger
2020-07-08 10:44 ` chao hao
2020-07-08 10:44 ` chao hao
2020-07-08 10:44 ` chao hao
2020-07-08 10:44 ` chao hao
2020-07-03 4:41 ` Chao Hao [this message]
2020-07-03 4:41 ` [PATCH v6 04/10] iommu/mediatek: Setting MISC_CTRL register Chao Hao
2020-07-03 4:41 ` Chao Hao
2020-07-03 4:41 ` Chao Hao
2020-07-06 15:18 ` Matthias Brugger
2020-07-06 15:18 ` Matthias Brugger
2020-07-06 15:18 ` Matthias Brugger
2020-07-06 15:18 ` Matthias Brugger
2020-07-03 4:41 ` [PATCH v6 05/10] iommu/mediatek: Move inv_sel_reg into the plat_data Chao Hao
2020-07-03 4:41 ` Chao Hao
2020-07-03 4:41 ` Chao Hao
2020-07-03 4:41 ` Chao Hao
2020-07-03 4:41 ` [PATCH v6 06/10] iommu/mediatek: Add sub_comm id in translation fault Chao Hao
2020-07-03 4:41 ` Chao Hao
2020-07-03 4:41 ` Chao Hao
2020-07-03 4:41 ` Chao Hao
2020-07-06 15:20 ` Matthias Brugger
2020-07-06 15:20 ` Matthias Brugger
2020-07-06 15:20 ` Matthias Brugger
2020-07-06 15:20 ` Matthias Brugger
2020-07-03 4:41 ` [PATCH v6 07/10] iommu/mediatek: Add REG_MMU_WR_LEN_CTRL register definition Chao Hao
2020-07-03 4:41 ` Chao Hao
2020-07-03 4:41 ` Chao Hao
2020-07-03 4:41 ` Chao Hao
2020-07-10 13:49 ` Matthias Brugger
2020-07-10 13:49 ` Matthias Brugger
2020-07-10 13:49 ` Matthias Brugger
2020-07-10 13:49 ` Matthias Brugger
2020-07-03 4:41 ` [PATCH v6 08/10] iommu/mediatek: Extend protect pa alignment value Chao Hao
2020-07-03 4:41 ` Chao Hao
2020-07-03 4:41 ` Chao Hao
2020-07-03 4:41 ` Chao Hao
2020-07-03 4:41 ` [PATCH v6 09/10] iommu/mediatek: Modify MMU_CTRL register setting Chao Hao
2020-07-03 4:41 ` Chao Hao
2020-07-03 4:41 ` Chao Hao
2020-07-03 4:41 ` Chao Hao
2020-07-06 15:22 ` Matthias Brugger
2020-07-06 15:22 ` Matthias Brugger
2020-07-06 15:22 ` Matthias Brugger
2020-07-06 15:22 ` Matthias Brugger
2020-07-03 4:41 ` [PATCH v6 10/10] iommu/mediatek: Add mt6779 basic support Chao Hao
2020-07-03 4:41 ` Chao Hao
2020-07-03 4:41 ` Chao Hao
2020-07-03 4:41 ` Chao Hao
2020-07-10 14:13 ` [PATCH v6 00/10] MT6779 IOMMU SUPPORT Joerg Roedel
2020-07-10 14:13 ` Joerg Roedel
2020-07-10 14:13 ` Joerg Roedel
2020-07-10 14:13 ` Joerg Roedel
2020-07-11 7:11 ` Yong Wu
2020-07-11 7:11 ` Yong Wu
2020-07-11 7:11 ` Yong Wu
2020-07-11 7:11 ` Yong Wu
2020-07-13 13:29 ` Joerg Roedel
2020-07-13 13:29 ` Joerg Roedel
2020-07-13 13:29 ` Joerg Roedel
2020-07-13 13:29 ` Joerg Roedel
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